HIGH CURRENT DENSITY POWER FIELD EFFECT TRANSISTOR

• US 20090278176A1
• Filed: 05/12/2008
• Published: 11/12/2009
• Est. Priority Date: 05/12/2008
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Li, Jian, Owyang, King
• Granted Patent: US 8,269,263 B2
• Time in Patent Office: Days
• US Class Current: 257/262
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.

Claims

1. A hybrid power field effect transistor device, comprising:

a JFET component;

a first accumulation MOSFET disposed adjacent to the JFET component;

a second accumulation MOSFET disposed adjacent to the JFET component at the trench bottom end; and

wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are configured to induce current flow through bulk silicon regions of the device.

2. The device of claim 1, further comprising:

a first Schottkey region disposed on the side of the JFET component;

formed on a side wall of vertical contact trench, without connecting n+ source and p+ contact in an n-channel device.

3. The device of claim 1, wherein the first accumulation MOSFET and the second accumulation MOSFET include a thin oxide on a side trench wall and a thick gate oxide region near a trench bottom to reduce gate to drain capacitance.

4. The device of claim 1, wherein the first accumulation MOSFET and the second accumulation MOSFET are disposed in accordance with a high-density design layout to facilitate self aligned determination.

5. The device of claim 1, wherein the induced current flow through bulk silicon regions of the device is configured to reduce gate oxide scattering.

6. The device of claim 1, wherein the first accumulation MOSFET and the second accumulation MOSFET are N channel MOSFETS.

7. The device of claim 1, wherein the first accumulation MOSFET and the second MOSFET with an isolated gate connecting to the source.

8. The device of claim 1, wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are fabricated as a trench based a vertical device.

9. A power MOSFET device, comprising:

a JFET component;

a first accumulation MOSFET disposed adjacent to the JFET component;

a second accumulation MOSFET disposed adjacent to the JFET component on the side opposite the first accumulation MOSFET;

wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are configured to induce current flow through bulk silicon regions of the device; and

wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are fabricated as a trench based a vertical structure.

10. The device of claim 9, further comprising:

a first Schottkey region disposed on the side of the JFET component; and

a second Schottkey region disposed on the side of the JFET component opposite the first Schottkey region.

11. The device of claim 9, wherein the first accumulation MOSFET and the second accumulation MOSFET include a thick lower oxide gate region to reduce gate to drain capacitance.

12. The device of claim 9, wherein the first accumulation MOSFET and the second accumulation MOSFET are disposed in accordance with a high-density design layout to facilitate self aligned determination.

13. The device of claim 9, wherein the induced current flow through bulk silicon regions of the device is configured to reduce gate oxide scattering.

14. The device of claim 9, wherein the first accumulation MOSFET and the second accumulation MOSFET are N channel MOSFETS.

15. The device of claim 9, wherein the first accumulation MOSFET and the second accumulation MOSFET are P channel MOSFETS.

16. A power FET device, comprising:

a JFET component;

a first accumulation MOSFET disposed adjacent to the JFET component;

a second accumulation MOSFET disposed adjacent to the JFET component on the side opposite the first accumulation MOSFET;

a first Schottkey region disposed on the side of the JFET component;

a second Schottkey region disposed on the side of the JFET component opposite the first Schottkey region;

wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are configured to induce current flow through bulk silicon regions of the device.

17. The device of claim 16, wherein the first accumulation MOSFET and the second accumulation MOSFET include a thick lower oxide gate region to reduce gate to drain capacitance.

18. The device of claim 16, wherein the first accumulation MOSFET and the second accumulation MOSFET are disposed in accordance with a high-density design layout to facilitate self aligned determination.

19. The device of claim 16, wherein the induced current flow through bulk silicon regions of the device is configured to reduce gate oxide scattering.