SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20090278178A1
• Filed: 10/16/2008
• Published: 11/12/2009
• Est. Priority Date: 10/17/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Kawahara, Jun, Yamamoto, Hironori, Hayashi, Yoshihiro, Ueki, Makoto
• Application Number:
  US12/445,996
• Publication Number:
  US 20090278178A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a semiconductor device which includes a MIS FET on a surface of a substrate, an insulating film on the substrate to cover the MIS FET, an opening that gets to an impurity diffusing region formed in the insulating film, another opening that gets to a gate electrode or to an extension part of the gate electrode formed in the insulating film, and an electrically conductive member including mainly copper filled in each of the openings. The insulating film includes a layer including, as main components, silicon, oxygen, carbon and hydrogen (FIG. 1).

Claims

1. A semiconductor device comprising:

a substrate;

a MIS FET provided on a surface of the substrate;

an insulating film provided on the substrate to cover the MIS FET;

an opening formed in the insulating film, the opening getting to an impurity diffusing region of the MIS FET;

another opening formed in the insulating film, the another opening getting to a gate electrode of the MIS FET or to an extension part of the gate electrode; and

an electrically conductive member filled into each of the openings, the electrically conductive member including, as a main component, copper;

the insulating film including a layer comprising, as main components, silicon, oxygen, carbon and hydrogen.

2. The semiconductor device according to claim 1, wherein the insulating film has a multi-layered structure, at least one layer of the multi-layered structure including, as main components, silicon, oxygen, carbon and hydrogen.

3. The semiconductor device according to claim 1, wherein the insulating film has a multi-layered structure;

at least the lowermost layer of the multi-layered structure including, as main components, silicon, oxygen, carbon and hydrogen.

4. The semiconductor device according to claim 1, wherein the insulating film includes an opening getting to a region astride the impurity diffusing region and the gate electrode of the MIS FET.

5. The semiconductor device according to claim 1, wherein the openings get to the impurity diffusing region and to the gate electrode or the extension part of the gate electrode of the MIS FET from an interconnect arranged in the insulating film.

6. The semiconductor device according to claim 1, wherein a barrier layer is provided on an inner wall of the opening.

7. The semiconductor device according to claim 1, wherein the layer comprising, as main components, silicon, oxygen, carbon and hydrogen, includes amorphous carbon and unsaturated hydrocarbons.

8. The semiconductor device according to claim 7, wherein the amorphous carbon includes an atom of sp² hybrid orbitals and an atom of sp³ hybrid orbitals.

9. The semiconductor device according to claim 1, wherein the insulating film has a metal wall getting to the substrate from the surface of the insulating film to surround the MIS FET.

16. The semiconductor device according to claim 1, wherein a gate insulating film between the substrate and the gate electrode in the MIS FET has a single-layer structure or a multi-layered structure.

17. The semiconductor device according to claim 1, wherein the extension part of the gate electrode is arranged at a position along the width-wise direction of the gate electrode;

and wherein

the gate electrode is extended along the gate width direction beyond the impurity diffusing region to get to the extension part of the gate electrode.

20. The semiconductor device according to claim 1, wherein, in the insulating film,

the layer including, as main components, Si (silicon)-O (oxygen)-C (carbon)-H (hydrogen) includes

Si:

O;

C;

H with a composition ratio equal to 1.0;

1.5;

1.0;

4.0,

O, C and H, out of the four elements, being in a range of approximately 20% from the composition ratio, respectively.

21. The semiconductor device according to claim 9, comprising

two or more folds of the metal walls extending from the surface of the insulating film to the substrate,

the two or more folds of the metal walls having, as a shape seen from the upper surface of the substrate, at least one of:

a ring shape spaced apart from each other;

a lattice shape; and

a shape in which a plurality of cross-pieces arranged in a staggered relationship between two neighboring metal wall, the cross-pieces interconnecting the neighboring metal walls.

23. The semiconductor device according to claim 1, wherein the gate electrode has a surface metalized and a portion on the gate insulating film thereof metalized.

25. The semiconductor device according to claim 1, wherein a contact of the opening on top of the gate electrode has a slit shape extended along the gate width direction.

10. A method for fabricating a semiconductor device comprising:

(a) depositing an insulating film including, as main components, silicon, oxygen, carbon and hydrogen, on a substrate on which a MIS FET is provided, so as to cover the MIS FET;

(b) forming, in the insulating film, an opening getting to an impurity diffusing region of the MIS FET and another opening getting to a gate electrode of the MIS FET or an extension part of the gate electrode;

(c) depositing a barrier layer and a seed layer in this order on an inner wall of the opening;

(d) filling an electrically conductive member including, as a main component, copper, in each of the openings; and

(e) removing the electrically conductive member on the insulating film so that an upper surface of the insulating film will be flush with an upper surface of the electrically conductive member.

12. The method according to claim 10, wherein in depositing the insulating film, the deposition is carried out by a plasma chemical vapor deposition method.

13. The method according to claim 10, wherein in depositing the insulating film, helium is used as a carrier gas.

14. The method according to claim 10, wherein in depositing the insulating film, a compound represented by the following formula (1) is used a raw material,

wherein R1 is any one of a vinyl group, a propenyl group and an isopropenyl group;

R2 is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group and an isobutyl group; and

R3 is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group and an isobutyl group.

15. The method for fabricating a semiconductor device according to claim 14, wherein the compound is isopropyl dimethoxyvinyl siloxane represented by the following formula (2).

18. The method according to claim 10, wherein a gate insulating film between the substrate and the gate electrode in the MIS FET has a single-layer structure or a multi-layered structure.

19. The method according to claim 10, wherein the extension part of the gate electrode is arranged at a position along the width-wise direction of the gate electrode in a spaced-apart relationship with respect to the impurity diffusing region;

and wherein

the gate electrode is extended along the gate width direction beyond the impurity diffusing region to get to the extension part of the gate electrode.

26. The method according to claim 10, wherein,

in the insulating film, the layer including, as main components, Si (silicon)-O (oxygen)-C (carbon)-H (hydrogen) includes

Si:

O;

C;

H with a composition ratio equal to 1.0;

1.5;

1.0;

4.0,

O, C and H, out of the four elements, being in a range of approximately 20% from the composition ratio, respectively.

11. A method for fabricating a semiconductor device comprising:

(a) depositing an insulating film including, as main components, silicon, oxygen, carbon and hydrogen, on a semiconductor substrate oil which a MIS FET is provided, so as to cover the MIS FET;

(a′

) forming an interconnect layer insulating film on the insulating layer;

(b) forming, in the insulating film and in the interconnect layer insulating film, an opening getting to an impurity diffusing region of the MIS FET and another opening getting to a gate electrode or to an extension part of the gate electrode;

(c) depositing a barrier layer and a seed layer in this order on an inner wall of the opening;

(d) filling an electrically conductive member including, as a main component, copper, in each of the openings; and

(e) removing the electrically conductive member on the interconnect layer insulating film so that an upper surface of the interconnect layer insulating film will be flush with an upper surface of the electrically conductive member in the opening.

22. The semiconductor device according to clam 1, wherein a metal compound is formed on a surface of the impurity diffusing region and on a surface of the gate electrode.

24. The semiconductor device according to clam 1, wherein a contact of the opening on top of the impurity diffusing region has a slit shape.