NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20090278193A1
• Filed: 05/01/2009
• Published: 11/12/2009
• Est. Priority Date: 05/09/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Murata, Takeshi, Kamigaichi, Takeshi
• Granted Patent: US 8,026,546 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.

Claims

1. A nonvolatile semiconductor memory device comprising:

a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate; and

a second stack unit with a first insulating layer and a first conductive layer alternately stacked on the upper surface of the first stack unit,

the second stack unit including

a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer,

a charge storage layer formed in contact with the second insulating layer for storing electrical charges,

a third insulating layer formed in contact with the charge storage layer, and

a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

the first semiconductor layer has an inverted U-shaped cross sectional shape in a way of turning back at an upper portion in the stacking direction and contacting the first selection transistor and the second selection transistor at a lower portion.

3. The nonvolatile semiconductor memory device according to claim 2, further comprising

a buried insulating film filling the inverted U-shaped portion of the first semiconductor layer.

4. The nonvolatile semiconductor memory device according to claim 1, wherein

the first selection transistor and the second selection transistor are planar-type transistor with the diffusion layer on the semiconductor substrate.

5. The nonvolatile semiconductor memory device according to claim 1, further comprising

a third stack unit positioned on the second stack unit, wherein

the third stack unit includes:

a first contact plug layer connected to the other diffusion layer of the first selection transistor;

a first wiring layer formed in contact with the first contact plug layer, extending in a first direction orthogonal to the stacking direction;

a second contact plug layer connected to the other diffusion layer of the second selection transistor; and

a second wiring layer formed in contact with the second contact plug layer, extending in a second direction orthogonal to the first direction in a main plane of the semiconductor substrate.

6. The nonvolatile semiconductor memory device according to claim 1, wherein

the first conductive layer is formed of partially silicided polysilicon.

7. The nonvolatile semiconductor memory device according to claim 1, wherein

the first semiconductor layer is formed of partially silicided polysilicon.

8. The nonvolatile semiconductor memory device according to claim 1, further comprising

a trench penetrating the second stack unit and reaching to the first stack unit, wherein

the second insulating layer, the charge storage layer, the third insulating layer, and the first semiconductor layer are formed in contact with the side walls of the first insulating layer and the first conductive layer facing the trench, and

the first selection transistor and the second selection transistor are insulation-separated by the insulating layer buried in the trench.

9. The nonvolatile semiconductor memory device according to claim 1, wherein

the first semiconductor layer has a U-shaped cross sectional shape in a trench penetrating the second stack unit and reaches to the first stack unit, and

the first semiconductor layer is connected to the diffusion layers of the first selection transistor and the second selection transistor respectively through a third contact plug layer and a fourth contact plug layer.

10. The nonvolatile semiconductor memory device according to claim 8, wherein

a bottom of the trench reaches to a portion inside the semiconductor substrate.

11. A nonvolatile semiconductor memory device having a plurality of NAND cell units formed of a plurality of electrically rewritable memory cells connected in series and the first selection transistor and the second selection transistor connected to both ends of the memory cells, respectively,

the NAND cell unit being formed by connecting a plurality of vertical-typed memory cells in a stacking direction, the memory cells having a channel region formed in a direction vertical to a surface of a substrate,

the first selection transistor and the second selection transistor being formed on a semiconductor substrate,

the channel region of the memory cell being formed by a first semiconductor layer formed so as to extend in the stacking direction with one end connected to a diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor, and

the first semiconductor layer having an inverted U-shaped cross sectional shape in a way of turning back at an upper portion in the stacking direction and contacting the first selection transistor and the second selection transistor at a lower portion.

12. The nonvolatile semiconductor memory device according to claim 11, further comprising

a buried insulating film which fills the inverted U-shaped portion of the first semiconductor layer.

13. The nonvolatile semiconductor memory device according to claim 11, wherein

the first selection transistor and the second selection transistor are planar-type transistor with the diffusion layer on the semiconductor substrate.

14. The nonvolatile semiconductor memory device according to claim 12, wherein

the first selection transistor and the second selection transistor are isolated by the buried insulating film filling the inverted U-shaped portion.

15. A method of manufacturing a nonvolatile semiconductor memory device, comprising:

forming a first selection transistor and a second selection transistor on a semiconductor substrate;

depositing a plurality of first insulating layers and a plurality of first conductive layers alternately on the upper surface of the first selection transistor and the second selection transistor;

forming a first opening by piercing the stacked first insulating layers and first conductive layers;

stacking a second insulating layer, a charge storage layer of storing electrical charges, and a third insulating layer by turns on a side surface of the first insulating layers and the first conductive layers facing the first opening; and

forming a first semiconductor layer of first conductive type in contact with the third insulating layer in a way of extending in a stacking direction;

the first semiconductor layer being formed in a way that one end is connected to a diffusion layer of the first selection transistor and the other end is connected to a diffusion layer of the second selection transistor.

16. The method of manufacturing the nonvolatile semiconductor memory device according to claim 15, wherein

the first semiconductor layer has an inverted U-shaped cross sectional shape in a way of turning back at an upper portion in the stacking direction and contacting the first selection transistor and the second selection transistor at a lower portion.

17. The method of manufacturing the nonvolatile semiconductor memory device according to claim 15, wherein

the first selection transistor and the second selection transistor are formed as a planar-type transistor having the diffusion layer on the semiconductor substrate.

18. The method of manufacturing the nonvolatile semiconductor memory device according to claim 15, further comprising

forming a second opening in the first semiconductor layer after forming the semiconductor layer having a first conductive type, and

burying an insulating film in the second opening.

19. The method of manufacturing the nonvolatile semiconductor memory device according to claim 15, further comprising

siliciding the first semiconductor layer.

20. The method of manufacturing the nonvolatile semiconductor memory device according to claim 18, further comprising

etching an upper surface of the insulating film to a portion higher than an upper surface of the uppermost first conductive layer after burying the insulating film in the second opening.