FinFETs having dielectric punch-through stoppers

• US 20090278196A1
• Filed: 05/06/2008
• Published: 11/12/2009
• Est. Priority Date: 05/06/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Cheng-Hung, Yeh, Chen-Nan
• Granted Patent: US 8,106,459 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and

a multiple-gate transistor on a second portion of the semiconductor substrate, wherein the second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor, and wherein the fin is electrically isolated from the semiconductor substrate by an insulator.

2. The semiconductor structure of claim 1, wherein the insulator electrically separates an additional fin underlying the fin, and wherein the additional fin and the fin are portions of a same fin.

3. The semiconductor structure of claim 1, wherein the multiple-gate transistor is a FinFET.

4. The semiconductor structure of claim 1, wherein the multiple-gate transistor is an Omega transistor.

5. The semiconductor structure of claim 1 further comprising an under-cut oxidation region under a top surface of an active region of the planar transistor, wherein the under-cut oxidation region extends into sidewalls of the active region, and wherein the under-cut oxidation region does not isolate the active region from the semiconductor substrate.

6. The semiconductor structure of claim 1, wherein a second top surface of the fin is substantially leveled with the first top surface.

7. The semiconductor structure of claim 1 further comprising a first subset of multiple-gate transistors having a first pitch, and a second subset of multiple-gate transistors having a second pitch greater than the first pitch, and wherein the first subset of multiple-gate transistors have a first fin height greater than a second fin height of the second subset of multiple-gate transistors.

8. The semiconductor structure of claim 1 further comprising:

a stressor region forming a ring encircling an active region of the planar transistor;

a buffer oxide separating the stressor region from the active region of the planar transistor; and

an isolation region encircling the stressor region, wherein the isolation region and the stressor region are formed of different materials.

9. The semiconductor structure of claim 1, wherein the insulator has a non-uniform thickness.

10. A semiconductor structure comprising:

a semiconductor substrate;

an isolation region over the semiconductor substrate and having a bottom surface, wherein the isolation region comprises a first portion having a first top surface and a second portion having a second top surface lower than the first top surface;

a first active region adjacent the first portion of the isolation region, wherein a top surface of the first active region is substantially leveled with the first top surface;

a second active region adjacent the second portion of the isolation region, wherein the second active region has a top surface higher than the second top surface;

an insulator separating the second active region into a top portion and a bottom portion electrically disconnected from each other;

a planar transistor on the first active region; and

a multiple-gate transistor having the top portion of the second active region as source/drain and channel regions.

11. The semiconductor structure of claim 10 further comprising an under-cut oxidation region lower than the top surface of the first active region, wherein the under-cut oxidation region extends into sidewalls of the active region, and wherein the under-cut oxidation region does not isolate the active region from the semiconductor substrate.

12. The semiconductor structure of claim 10 further comprising:

a silicon nitride ring encircling the first active region, wherein the silicon nitride ring adjoins the first portion of the isolation region; and

a buffer oxide separating the silicon nitride ring from the first active region.

13. A method of forming a semiconductor structure, the method comprising:

providing a semiconductor substrate;

forming an isolation region in the semiconductor substrate, wherein the isolation region encircles an active region;

recessing a top portion of the isolation region to expose sidewalls of the active region; and

at a level between a top surface of the active region and a bottom surface of the isolation region, oxidizing an intermediate portion of the active region to form an insulator layer separating the active region into a top portion and a bottom portion.

14. The method of claim 13, wherein the step of oxidizing the intermediate portion of the active region comprises:

forming a cap to mask sidewalls of the top portion of the active region;

etching the top portion of the isolation region to expose the portions of the sidewalls of the active region unmasked by the cap; and

oxidizing the exposed portions of the sidewalls of the active region to form the insulator layer.

15. The method of claim 14, wherein the step of etching the top portion of the isolation region comprises isotropic etching.

16. The method of claim 14, wherein the step of recessing the top portion of the isolation region is performed using a photoresist.

17. The method of claim 14, wherein the step of recessing the top portion of the isolation region is performed without using a photoresist.

18. The method of claim 13 further comprising, before the step of oxidizing the intermediate portion of the active region:

blanket forming a mask layer; and

removing a joint portion between a vertical portion and a horizontal portion of the mask layer to form an opening, wherein the vertical portion of the mask layer is on the sidewalls of the active region.

19. The method of claim 18 further comprising, before the step of oxidizing the intermediate portion of the active region, implanting oxygen ions into the intermediate portion of the active region through the opening.