DEVICE AND TECHNIQUE FOR TRANSISTOR WELL BIASING

• US 20090278571A1
• Filed: 05/06/2008
• Published: 11/12/2009
• Est. Priority Date: 05/06/2008
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pietri, Stefano, Olmos, Alfredo, Refaeli, Jehoda
• Granted Patent: US 8,164,378 B2
• Time in Patent Office: Days
• US Class Current: 327/50
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Claims

1. A method comprising:

receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage; and

biasing a well of a transistor based on the extreme voltage of the set of voltages.

2. The method of claim 1, wherein biasing the well of the transistor based on the extreme voltage comprises coupling the well of the transistor to a source of the extreme voltage of the set of voltages.

3. The method of claim 1, wherein biasing the well of the transistor based on the extreme voltage comprises:

concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage; and

selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage.

4. The method of claim 3, wherein:

the extreme voltage is the highest voltage of the set of voltages; and

providing the first signal and the second signal comprises;

configuring the first signal to have a voltage equal to the first voltage and the second signal to have a ground voltage in response to the first voltage being higher than the second voltage; and

configuring the second signal to have a voltage equal to the second voltage and the first signal to have the ground voltage in response to the second voltage being higher than the first voltage.

5. The method of claim 4, wherein selectively coupling comprises:

selectively coupling a source of the first voltage to the well of the transistor responsive to the second signal having the ground voltage and the third voltage being less than the first voltage;

selectively coupling a source of the second voltage to the well of the transistor responsive to the first signal having the ground voltage and the third voltage being less than the second voltage; and

selectively coupling a source of the third voltage to the well of the transistor responsive to the third voltage being greater than the first voltage and greater than the second voltage.

6. The method of claim 1, further comprising:

generating, at a voltage regulator, the third voltage based on the first voltage, the transistor comprising a power transistor of the voltage regulator.

7. The method of claim 1, wherein:

the transistor comprises a p-type transistor; and

the extreme voltage of the set of voltages comprises the highest voltage of the set of voltages.

8. The method of claim 1, wherein:

the transistor comprises an n-type transistor; and

the extreme voltage of the set of voltages comprises the lowest voltage of the set of voltages.

9. The method of claim 1, further comprising:

powering a set of one or more transistors using the extreme voltage of the set of voltages; and

biasing wells of the set of one or more transistors using the extreme voltage of the set of voltages.

10. An electronic device comprising:

a transistor; and

a power switching module comprising;

a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage; and

an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

11. The electronic device of claim 10, wherein the power switching module is configured to couple the well of the transistor to a source of the extreme voltage of the set of voltages.

12. The electronic device of claim 11, wherein the power switching module comprises:

a comparator comprising a first input to receive the first voltage, a second input to receive the second voltage, a first output to provide a first signal and a second output to provide a second signal, the comparator to configure the first signal and the second signal based on a comparison of the first voltage and the second voltage; and

a switch circuit comprising a first input coupled to the first output of the comparator, a second input coupled to the second output of the comparator, and an output coupled to the output of the power switching module, the switch circuit configured to selectively couple the output of the power switching module to a source of the one of the first voltage, the second voltage or the third voltage based on first signal, the second signal, and the third voltage.

13. The electronic device of claim 12, wherein:

the extreme voltage is the highest voltage of the set of voltages; and

the comparator is configured to;

configure the first signal to have a voltage equal to the first voltage and the second signal to have a ground voltage in response to the first voltage being higher than the second voltage; and

configure the second signal to have a voltage equal to the second voltage and the first signal to have the ground voltage in response to the second voltage being higher than the first voltage.

14. The electronic device of claim 13, wherein the switch circuit is configured to:

selectively couple a source of the first voltage to the well of the transistor responsive to the second signal having the ground voltage and the third voltage being less than the first voltage;

selectively couple a source of the second voltage to the well of the transistor responsive to the first signal having the ground voltage and the third voltage being less than the second voltage; and

selectively couple a source of the third voltage to the well of the transistor responsive to the third voltage being greater than the first voltage and greater than the second voltage.

15. The electronic device of claim 13, wherein:

the switch circuit comprises;

a first transistor comprising a gate electrode coupled to the first input, a source electrode coupled to a source of the third voltage, a drain electrode, and a body coupled to the output of the power switching module;

a second transistor comprising a gate electrode coupled to the second input, a source electrode coupled to the drain electrode of the first transistor, a drain electrode coupled to the first input, and a body coupled to the output of the power switching module;

a third transistor comprising a gate electrode coupled to the second input, a source electrode coupled to the source of the third voltage, a drain electrode, and a body coupled to the output of the power switching module;

a fourth transistor comprising a gate electrode coupled to the first input, a source electrode coupled to the drain electrode of the third transistor, a drain electrode coupled to the second input, and a body coupled to the output of the power switching module;

a fifth transistor comprising a gate electrode coupled to the second input, a source electrode coupled to a source of the first voltage, a drain electrode coupled to the output of the power switching module, and a body coupled to the output of the power switching module;

a sixth transistor comprising a gate electrode coupled to the first input, a source electrode coupled to a source of the second voltage, a drain electrode coupled to the output of the power switching module, and a body coupled to the output of the power switching module;

a seventh transistor comprising a gate electrode coupled to the source of the first voltage, a source electrode coupled to the source of the third voltage, a drain electrode, and a body coupled to the output of the power switching module; and

an eighth transistor comprising a gate electrode coupled to the source of the second voltage, a source electrode coupled to the drain electrode of the seventh transistor, a drain electrode coupled to the output of the power switching module, and a body coupled to the output of the power switching module.

16. The electronic device of claim 10, further comprising:

a voltage regulator comprising the transistor.

17. The electronic device of claim 16, wherein the voltage regulator comprises:

an input to receive the first voltage and an output to provide the third voltage based on the first voltage using the transistor.

18. The electronic device of claim 10, further comprising:

retention circuitry comprising an input coupled to the output of the power switching circuit, the retention circuitry comprising a set of one or more transistors powered by the extreme voltage and having wells biased by the extreme voltage.

19. The electronic device of claim 10, wherein:

the transistor comprises a p-type transistor; and

the extreme voltage of the set of voltages comprises the highest voltage of the set of voltages.

20. The electronic device of claim 10, wherein:

the transistor comprises an n-type transistor; and

the extreme voltage of the set of voltages comprises the lowest voltage of the set of voltages.