NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array

• US 20090279360A1
• Filed: 05/07/2009
• Published: 11/12/2009
• Est. Priority Date: 05/07/2008
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya, Hsu, Fu-Chang
• Granted Patent: US 8,072,811 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

Claims

1. A NOR flash nonvolatile memory circuit comprising:

a plurality of charge retaining transistors serially connected in a NAND string;

wherein a drain of a topmost charge retaining transistor is connected to a bit line associated with the plurality of serially connected charge retaining transistors;

wherein a source of a bottommost charge retaining transistor is connected to a source line associated with the plurality of charge retaining transistors; and

wherein a control gate of each of the plurality of charge retaining transistors is connected to a word line.

2. The NOR flash nonvolatile memory circuit of claim 1 wherein the plurality of charge retaining transistors are formed within a well of a first conductivity type

3. The NOR flash nonvolatile memory circuit of claim 2 wherein the well of the first conductivity type is formed within a deep well of a second conductivity type.

4. The NOR flash nonvolatile memory circuit of claim 3 wherein the deep well of the second conductivity type is formed in a substrate of the first conductivity type

5. The NOR flash nonvolatile memory circuit of claim 1 wherein the plurality of charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

6. The NOR flash nonvolatile memory circuit of claim 1 wherein a selected charge retaining transistor of the plurality of charge retaining transistors is programmed as single-level program cell by applying a very high program voltage level of from approximately +15.0V to approximately +20.0V in incrementally increasing steps between the control gate of the selected charge retaining transistor and a bulk region of the charge retaining transistor.

7. The NOR flash nonvolatile memory circuit of claim 6 wherein non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by applying an intermediate program inhibit voltage level of less than 10.0V between the control gate of the non-selected charge retaining transistors and a bulk region of the non-selected charge retaining transistors.

8. The NOR flash nonvolatile memory circuit of claim 1 wherein a layout of the NOR flash memory circuit is such that the size of the NOR flash memory circuit is of from approximately four times to approximately six times the minimum feature size (λ

) of the process technology for fabricating the NOR flash memory circuit.

9. The NOR flash nonvolatile memory circuit of claim 1 wherein the selected charge retaining transistor is erased by applying a very high positive erase voltage level of from approximately +15.0 v to approximately +20.0V between the a bulk region of the selected charge retaining transistor and control gate of selected the charge retaining transistor.

10. The NOR flash nonvolatile memory circuit of claim 1 wherein non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by biasing the non-selected charge retaining transistors such that there is a approximately a 0.0V voltage level between the control gate and the bulk region of the non-selected storage transistors.

11. The NOR flash nonvolatile memory circuit of claim 1 the selected charge retaining transistor of the plurality of charge retaining transistors that is programmed as a single-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistors within the NOR flash memory circuit is set to a voltage level of a power supply voltage source;

the gate of the non-selected charge retaining transistor within the plurality of charge retaining transistors is set to a first very high read voltage; and

comparing a voltage developed at the source line in the voltage follower sensing circuit with reference voltage source. The reference voltage source is set to a reference voltage level of approximately 2.0V to distinguish between a threshold voltage level for a first logic level and a threshold voltage levels of a second logic level.

12. The NOR flash nonvolatile memory circuit of claim 11 wherein the first very high read voltage is greater than 6.0V.

13. The NOR flash nonvolatile memory circuit of claim 11 wherein the reference voltage level is approximately 2.0V.

14. The NOR flash nonvolatile memory circuit of claim 11 wherein if the NOR flash nonvolatile memory circuit is not selected for reading when another NOR flash nonvolatile memory circuit is selected in an array NOR flash nonvolatile memory circuits, the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit is set to the ground reference voltage to turn off the charge retaining transistors.

15. The NOR flash nonvolatile memory circuit of claim 1 wherein the selected charge retaining transistor of the plurality of charge retaining transistors that is programmed as a multi-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistor to a moderately high voltage level;

setting the gate of all non-selected charge retaining transistors within the plurality of charge retaining transistors to a second very high read voltage; and

comparing a voltage developed at the source line in the voltage follower sensing circuit to a number of reference voltage levels to determine a threshold voltage representing data stored within the charge retaining transistor.

16. The NOR flash nonvolatile memory circuit of claim 15 wherein the moderately high voltage level is approximately +4.0V

17. The NOR flash nonvolatile memory circuit of claim 15 where in the second very high read voltage is greater than 7.0V.

18. The NOR flash nonvolatile memory circuit of claim 15 wherein the reference voltage levels are set to between each of the voltage threshold levels that distinguish between the threshold voltage levels for each datum stored in the charge retaining transistor.

19. The NOR flash nonvolatile memory circuit of claim 15 wherein if the NOR flash nonvolatile memory circuit is not selected for reading when another NOR flash nonvolatile memory circuit is selected in an array NOR flash nonvolatile memory circuits, the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit is set to the ground reference voltage to turn off the charge retaining transistors.

20. A NOR flash nonvolatile memory device comprising:

an array of a plurality of NOR flash nonvolatile memory circuits arranged in rows and column, wherein each of the nonvolatile memory circuits comprise;

a plurality of charge retaining transistors on each column are connected serially in a NAND string;

wherein a drain of a topmost charge retaining transistor of each NOR flash memory circuit is connected to a local bit line associated with the column on which each NOR flash memory circuit resides;

wherein a source of a bottommost charge retaining transistor of each of the NOR flash memory circuits is connected to a local source line associated with the on which each NOR flash memory circuit; and

wherein each control gate of the charge retaining transistors on each row are commonly connected to a word line.

21. The NOR flash nonvolatile memory device of claim 20 wherein the bit lines and the source lines are associated with a column of the NOR flash nonvolatile memory circuits and are parallel.

22. The NOR flash nonvolatile memory device of claim 20 further comprising a column voltage control circuit connected to provide control signals to local bit lines and the source lines associated with each of the columns of charge retaining transistors.

23. The NOR flash nonvolatile memory device of claim 22 wherein each of the local bit lines is connected to one of a plurality of global bit lines through a bit line select transistor.

24. The NOR flash nonvolatile memory device of claim 23 wherein each of the local source lines is connected to one of a plurality of global source lines through a source line select transistor.

25. The NOR flash nonvolatile memory device of claim 24 wherein the global bit lines and the global source lines are connected to the column voltage control circuit to transfer the control signals to selected local bit lines and selected local source lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits.

26. The NOR flash nonvolatile memory device of claim 20 further comprising a row voltage control circuit connected to provide control signals to word lines associated with each of the rows of charge retaining transistors.

27. The NOR flash nonvolatile memory device of claim 26 wherein the row control circuit transfers the control signals to word lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits.

28. The NOR flash nonvolatile memory device of claim 25 further comprising a bit line select control circuit connected the gates of the local bit line select transistors and the source line select transistors connected to each of the local bit lines.

29. The NOR flash nonvolatile memory device of claim 20 wherein the row control circuit transfers word line control signals to word lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits and bit line select signals to the selected bit line select transistors and source line select signals to the selected source line transistors to transfer the bit line and source line control signals from the column voltage control circuit to the selected local bit lines and selected local source lines.

30. The NOR flash nonvolatile memory device of claim 20 wherein the plurality of charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

31. The NOR flash nonvolatile memory device of claim 20 wherein a selected charge retaining transistor of the plurality of charge retaining transistors is programmed as single-level program cell by applying a very high program voltage level of from approximately +15.0V to approximately +20.0V in incrementally increasing steps between the control gate of the selected charge retaining transistor and a bulk region of the charge retaining transistor.

32. The NOR flash nonvolatile memory device of claim 31 wherein non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by applying an intermediate program inhibit voltage level of less than 10.0V between the control gate of the non-selected charge retaining transistors and a bulk region of the non-selected charge retaining transistors.

33. The NOR flash nonvolatile memory device of claim 20 wherein a layout of the NOR flash memory circuit is such that the size of the NOR flash memory circuit is of from approximately four times to approximately six times the minimum feature size (λ

) of the process technology for fabricating the NOR flash memory circuit.

34. The NOR flash nonvolatile memory device of claim 20 wherein the selected charge retaining transistor is erased by applying a very high negative erase voltage level of from approximately +15.0V to approximately +20.0V between the a bulk region of the selected charge retaining transistor and control gate of the selected charge retaining transistor.

35. The NOR flash nonvolatile memory device of claim 20 wherein non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by biasing the non-selected charge retaining transistors such that there is a approximately a 0.0V voltage level between the control gate and the bulk region of the non-selected storage transistors.

36. The NOR flash nonvolatile memory device of claim 20 wherein the selected charge retaining transistor of the plurality of charge retaining transistors that is programmed as a single-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistors within the NOR flash memory circuit is set to a voltage level of a power supply voltage source;

the gate of the non-selected charge retaining transistor within the plurality of charge retaining transistors is set to a first very high read voltage; and

comparing a voltage developed at the source line in the voltage follower sensing circuit with reference voltage source. The reference voltage source is set to a reference voltage level of approximately 2.0V to distinguish between a threshold voltage level for a first logic level and a threshold voltage levels of a second logic level.

37. The NOR flash nonvolatile memory device of claim 36 wherein the first very high read voltage is greater than 6.0V.

38. The NOR flash nonvolatile memory device of claim 36 wherein the reference voltage level is approximately 2.0V.

39. The NOR flash nonvolatile memory device of claim 36 wherein the word lines and thus the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit are set to the ground reference voltage to turn off the charge retaining transistors.

40. The NOR flash nonvolatile memory device of claim 20 wherein the selected charge retaining transistor of the plurality of charge retaining transistors programmed as a multi-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistor to a moderately high voltage level;

setting the gate of all non-selected charge retaining transistors within the plurality of charge retaining transistors to a second very high read voltage and

comparing a voltage developed at the source line in the voltage follower sensing circuit to a number of reference voltage levels to determine a threshold voltage representing data stored within the charge retaining transistor.

41. The NOR flash nonvolatile memory device of claim 40 wherein the moderately high voltage level is approximately +4.0V

42. The NOR flash nonvolatile memory device of claim 40 where in the second very high read voltage is greater than 7.0V.

43. The NOR flash nonvolatile memory device of claim 40 wherein the reference voltage levels are set to between each of the voltage threshold levels that distinguish between the threshold voltage levels for each datum stored in the charge retaining transistor.

44. The NOR flash nonvolatile memory device of claim 40 wherein the word lines and thus the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit are set to the ground reference voltage to turn off the charge retaining transistors.

45. A method for forming a NOR flash nonvolatile memory device comprises the steps of:

providing a substrate; and

forming an array of a plurality of NOR flash nonvolatile memory circuits configured in rows and columns, wherein for the NOR flash nonvolatile memory circuits are formed by the steps of;

forming a plurality of charge retaining transistors such that the charge retaining transistors are placed the rows and columns,

connecting the plurality of charge retaining transistors on a column serially in a NAND string,

connecting a drain of a topmost charge retaining transistor of each NOR flash memory circuit to a local bit line associated with the column on which each NOR flash memory circuit resides,

connecting a source of a bottommost charge retaining transistor of each of the NOR flash memory circuits to a local source line associated with the on which each NOR flash memory circuit, and

connecting each control gate of the charge retaining transistors on each row are commonly to a word line.

46. The method for forming a NOR flash nonvolatile memory device of claim 45 further comprising the steps of:

associating each column of the NOR flash nonvolatile memory circuits with the bit lines and source lines; and

arranging the bit lines and the source lines in parallel.

47. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein a layout of the NOR flash memory circuit is such that the size of the NOR flash memory circuit is of from approximately four times to approximately six times the minimum feature size (λ

) of the process technology for fabricating the NOR flash memory circuit.

48. The method for forming a NOR flash nonvolatile memory device of claim 45 further comprises the steps of:

forming a column voltage control circuit; and

connecting the column voltage control circuit to provide control signals to local bit lines and the source lines associated with each of the columns of charge retaining transistors.

49. The method for forming a NOR flash nonvolatile memory device of claim 48 further comprising the comprising the step of connecting each of the local bit lines to one of a plurality of global bit lines through a bit line select transistor,

50. The method for forming a NOR flash nonvolatile memory device of claim 45 further comprising the step of connecting each of the local source lines to one of a plurality of global source lines through a source line select transistor.

51. The method for forming a NOR flash nonvolatile memory device of claim 46 further comprising the step of connecting the global bit lines and the global source lines to the column voltage control circuit to transfer the control signals to selected local bit lines and selected local source lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits.

52. The method for forming a NOR flash nonvolatile memory device of claim 46 further comprises the step of forming a row voltage control circuit.

53. The method for forming a NOR flash nonvolatile memory device of claim 52 further comprising connecting the row voltage control circuit to provide control signals to word lines associated with each of the rows of charge retaining transistors.

54. The method for forming a NOR flash nonvolatile memory device of claim 52 further comprising connecting the gates of the local bit line select transistors and the source line select transistors connected to each of the local bit lines.

55. The method for forming a NOR flash nonvolatile memory device of claim 54 further comprising transferring from the row control circuit the control signals to word lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits.

56. The method for forming a NOR flash nonvolatile memory device of claim 55 further comprising transferring from the row voltage control circuit the select control signals to the selected bit line select transistors and the selected source line transistors to transfer the bit line and source line control signals from the column voltage control circuit to the selected local bit lines and selected local source lines.

57. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein the plurality of charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

58. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein a selected charge retaining transistor of the plurality of charge retaining transistors is programmed as single-level program cell by applying a very high program voltage level of from approximately +15.0V to approximately +20.0V in incrementally increasing steps between the control gate of the selected charge retaining transistor and a bulk region of the charge retaining transistor.

59. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by applying an intermediate program inhibit voltage level of less than 10.0V between the control gate of the non-selected charge retaining transistors and a bulk region of the non-selected charge retaining transistors.

60. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein the selected charge retaining transistor is erased by applying a very high negative erase voltage level of from approximately +15.0V to approximately +20.0V between the a bulk region of the selected charge retaining transistor and control gate of the selected charge retaining transistor.

61. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by biasing the non-selected charge retaining transistors such that there is a approximately a 0.0V voltage level between the control gate and the bulk region of the non-selected storage transistors.

62. The method for forming a NOR flash nonvolatile memory device of claim 45 the selected charge retaining transistor of the plurality of charge retaining transistors that is programmed as a single-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistors within the NOR flash memory circuit is set to a voltage level of a power supply voltage source;

the gate of the non-selected charge retaining transistor within the plurality of charge retaining transistors is set to a first very high read voltage; and

comparing a voltage developed at the source line in the voltage follower sensing circuit with reference voltage source. The reference voltage source is set to a reference voltage level of approximately 2.0V to distinguish between a threshold voltage level for a first logic level and a threshold voltage levels of a second logic level.

63. The method for forming a NOR flash nonvolatile memory device of claim 62 wherein the first very high read voltage is greater than 6.0V.

64. The method for forming a NOR flash nonvolatile memory device of claim 62 wherein the reference voltage level is approximately 2.0V.

65. The method for forming a NOR flash nonvolatile memory device of claim 62 wherein the word lines and thus the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit are set to the ground reference voltage to turn off the charge retaining transistors.

66. The method for forming a NOR flash nonvolatile memory device of claim 45 wherein the selected charge retaining transistor of the plurality of charge retaining transistors that is programmed as a multi-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistor to a moderately high voltage level;

setting the gate of all non-selected charge retaining transistors within the plurality of charge retaining transistors to a second very high read voltage; and

comparing a voltage developed at the source line in the voltage follower sensing circuit to a number of reference voltage levels to determine a threshold voltage representing data stored within the charge retaining transistor.

67. The method for forming a NOR flash nonvolatile memory device of claim 66 wherein the moderately high voltage level is approximately +4.0V

68. The method for forming a NOR flash nonvolatile memory device of claim 66 where in the second very high read voltage is greater than 7.0V.

69. The method for forming a NOR flash nonvolatile memory device of claim 66 wherein the reference voltage levels are set to between each of the voltage threshold levels that distinguish between the threshold voltage levels for each datum stored in the charge retaining transistor.

70. The method for forming a NOR flash nonvolatile memory device of claim 66 wherein the word lines and thus the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit are set to the ground reference voltage to turn off the charge retaining transistors.

71. An integrated circuit device comprising:

an array of NAND flash nonvolatile memory circuits, each of the NAND flash nonvolatile memory circuit comprising;

a plurality of charge retaining transistors arranged in rows and columns wherein said charge retaining transistors on each column form at least one grouping of charge retaining transistors that is arranged in a NAND series string of charge retaining transistors, each NAND series string having a top select transistor and a bottom select transistor;

an array of a plurality of NOR flash nonvolatile memory circuits, wherein each of the nonvolatile memory circuits comprise;

a plurality of charge retaining transistors arranged in rows and column wherein the charge retaining transistors on each column are organized into at least one grouping and each grouping of the charge retaining transistors are connected serially in a NAND string;

wherein a drain of a topmost charge retaining transistor of each NOR flash memory circuit is connected to a local bit line associated with the column on which each NOR flash memory circuit resides;

wherein a source of a bottommost charge retaining transistor of each of the NOR flash memory circuits is connected to a local source line associated with the on which each NOR flash memory circuit; and

wherein each control gate of the charge retaining transistors on each row are commonly connected to a word line.

72. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, wherein the bit lines and the source lines are associated with a column of the NOR flash nonvolatile memory circuits and are parallel.

73. The integrated circuit device of claim 71 wherein each of the NOR flash nonvolatile memory circuits further comprise a column voltage control circuit connected to provide control signals to local bit lines and the source lines associated with each of the columns of charge retaining transistors.

74. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, the local bit lines is connected to one of a plurality of global bit lines through a bit line select transistor.

75. The integrated circuit device of claim 74 wherein in each of the NOR flash nonvolatile memory circuits, the local source lines is connected to one of a plurality of global source lines through a source line select transistor.

76. The integrated circuit device of claim 75 wherein in each of the NOR flash nonvolatile memory circuits, the global bit lines and the global source lines are connected to the column voltage control circuit to transfer the control signals to selected local bit lines and selected local source lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits.

77. The integrated circuit device of claim 74 wherein each of the NOR flash nonvolatile memory circuits further comprises a row voltage control circuit connected to provide control signals to word lines associated with each of the rows of charge retaining transistors.

78. The integrated circuit device of claim 77 wherein in each of the NOR flash nonvolatile memory circuits, the row control circuit transfers the control signals to word lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits.

79. The integrated circuit device of claim 78 wherein in each of the NOR flash nonvolatile memory circuits further comprises a bit line select control circuit connected the gates of the local bit line select transistors and the source line select transistors connected to each of the local bit lines.

80. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, the row control circuit transfers word line control signals to word lines for reading, programming, and erasing selected charge retaining transistors within the NOR flash nonvolatile memory circuits and bit line select signals to the selected bit line select transistors and source line select signals to the selected source line transistors to transfer the bit line and source line control signals from the column voltage control circuit to the selected local bit lines and selected local source lines.

81. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, the plurality of charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

82. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, a selected charge retaining transistor of the plurality of charge retaining transistors is programmed as single-level program cell by applying a very high program voltage level of from approximately +15.0V to approximately +20.0V in incrementally increasing steps between the control gate of the selected charge retaining transistor and a bulk region of the charge retaining transistor.

83. The integrated circuit device of claim 82 wherein in each of the NOR flash nonvolatile memory circuits, non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by applying an intermediate program inhibit voltage level of less than 10.0V between the control gate of the non-selected charge retaining transistors and a bulk region of the non-selected charge retaining transistors.

84. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, a layout of the NOR flash memory circuit is such that the size of the NOR flash memory circuit is of from approximately four times to approximately six times the minimum feature size (λ

) of the process technology for fabricating the NOR flash memory circuit.

85. The integrated circuit device of claim 71.wherein in each of the NOR flash nonvolatile memory circuits, the selected charge retaining transistor is erased by applying a very high negative erase voltage level of from approximately +15.0V to approximately +20.0V between the a bulk region of the selected charge retaining transistor and control gate of the selected charge retaining transistor.

86. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, non-selected charge retaining transistors of the plurality of charge retaining transistors are inhibited by biasing the non-selected charge retaining transistors such that there is a approximately a 0.0V voltage level between the control gate and the bulk region of the non-selected storage transistors.

87. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, the selected charge retaining transistor of the plurality of charge retaining transistors that is programmed as a single-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistors within the NOR flash memory circuit is set to a voltage level of a power supply voltage source;

the gate of the non-selected charge retaining transistor within the plurality of charge retaining transistors is set to a first very high read voltage; and

comparing a voltage developed at the source line in the voltage follower sensing circuit with reference voltage source. The reference voltage source is set to a reference voltage level of approximately 2.0V to distinguish between a threshold voltage level for a first logic level and a threshold voltage levels of a second logic level.

88. The integrated circuit device of claim 87 wherein in each of the NOR flash nonvolatile memory circuits, the first very high read voltage is greater than 6.0V.

89. The integrated circuit device of claim 87 wherein in each of the NOR flash nonvolatile memory circuits, the reference voltage level is approximately 2.0V.

90. The integrated circuit device of claim 87 wherein the word lines and thus the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit are set to the ground reference voltage to turn off the charge retaining transistors.

91. The integrated circuit device of claim 71 wherein in each of the NOR flash nonvolatile memory circuits, the selected charge retaining transistor of the plurality of charge retaining transistors programmed as a multi-level program cell is read by:

connecting the source line to a voltage follower sensing circuit;

setting the gate and drain of the selected charge retaining transistor to a moderately high voltage level;

setting the gate of all non-selected charge retaining transistors within the plurality of charge retaining transistors to a second very high read voltage and

comparing a voltage developed at the source line in the voltage follower sensing circuit to a number of reference voltage levels to determine a threshold voltage representing data stored within the charge retaining transistor.

92. The integrated circuit device of claim 91 wherein in each of the NOR flash nonvolatile memory circuits, the moderately high voltage level is approximately +4.0V

93. The integrated circuit device of claim 91 wherein in each of the NOR flash nonvolatile memory circuits, the second very high read voltage is greater than 7.0V.

94. The integrated circuit device of claim 91 wherein in each of the NOR flash nonvolatile memory circuits, the reference voltage levels are set to between each of the voltage threshold levels that distinguish between the threshold voltage levels for each datum stored in the charge retaining transistor.

95. The integrated circuit device of claim 91 wherein the word lines and thus the control gates of the non-selected charge retaining transistors of the plurality of charge retaining transistors of non-selected NOR flash memory circuit are set to the ground reference voltage to turn off the charge retaining transistors.