Techniques for using dual memory structures for processing failure detection protocol packets

• US 20090279542A1
• Filed: 12/10/2007
• Published: 11/12/2009
• Est. Priority Date: 01/11/2007
• Status: Active Grant

• Current Assignee: Extreme Networks, Inc.
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Wong, Yuen, Moobed, Pedman
• Granted Patent: US 8,155,011 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 41/0631 using root cause analysis; using analysis of correlation between notifications, alarms or events based on decision criteria, e.g. hierarchy, tree or time analysis
• CPC Class Codes: H04L 43/0823 Errors, e.g. transmission errors

Abstract

Techniques are provided for assisting in the processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. The processing is performed using dual memory structures that enable receipt of FDP packets by the network device to be decoupled from the processing of FDP packets by the CPU of the network device.

Claims

1-21. -21. (canceled)

22. A bipolar transistor, comprising:

a collector provided in a single-crystal semiconductor region, said collector having an uppermost surface being a major surface extending in first and second directions defining a reference plane, said reference plane having a first portion, and a second portion extending outward from said first portion;

an intrinsic base aligned with said first portion and not aligned with said second portion;

an epitaxial spacer layer overlying said reference plane, said epitaxial spacer layer being aligned with said second portion and not aligned with said first portion;

an emitter overlying and aligned with said intrinsic base and said first portion; and

an extrinsic base overlying and aligned with said epitaxial spacer layer and not aligned with said intrinsic base.

23. The bipolar transistor as claimed in claim 24, wherein said epitaxial spacer layer has a first thickness and said first and second distances differ by an amount equal to said first thickness.

24. The bipolar transistor as claimed in claim 22, wherein said extrinsic base has a lower surface spaced a first distance from said reference plane and said intrinsic base has a lower surface spaced a second distance from said reference plane, said second distance being less than said first distance.

25. The bipolar transistor as claimied in claim 22, wherein said epitaxial spacer layer is not intentionally doped.

26. The bipolar transistor as claimed in claim 22, wherein said epitaxial spacer layer contains at most a very light dopant concentration.

27. The bipolar transistor as claimed in claim 22, wherein said collector region has a first dopant concentration,k said intrinsic base has a second dopant concentration, and said epitaxial spacer layer includes a semiconductor having a third dopant concentration which is lowe than both said first and second dopant concentrations.

28. The bipolar transistor as claimed in claim 22, wherein said intrinsic base includes an epitaxial layer consisting essentially of a semiconductor alloy.

29. The bipolar transistor as claimed in claim 28, wherein said collector consists essentially of silicon and said intrinsic base consists essentially of silicon germanium.

30. The bipolar transistor as claimed in claim 22, wherein said epitaxial spacer layer consists essentially of a semiconductor alloy layer having a lower dopant diffusion rate than silicon.

31. The bipolar transistor as claimed in claim 30, wherein said epitaxial spacer layer consists essentiallly of silicon carbon.

32. The bipolar transistor as claimed in claim 31, wherein said epitaxial spacer layer consists essentially of silicon germanium.

33. The bipolar transistor as claimed in claim 32, wherein said epitaxial spacer layr includes carbon incorporated into said silicon germanium.

34. The bipolar transistor as claimed in claim 22, wherein said extrinsic base is raised.

35. The bipolar transistor as claimed in claim 34, wherein said extrinsic base is self-aligned to said emitter.