PIPELINE METHOD AND SYSTEM FOR SWITCHING PACKETS
First Claim
1. In a switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure, a method for switching packets rapidly between one or more source devices and one or more destination devices, the method comprising:
- pipelining packets through a series of first processing segments to perform a plurality of first sub-operations involved in initial processing of packets received from source devices to be buffered in the memory structure;
pipelining packets through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission; and
pipelining packets through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.
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Accused Products
Abstract
A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.
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Citations
21 Claims
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1. In a switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure, a method for switching packets rapidly between one or more source devices and one or more destination devices, the method comprising:
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pipelining packets through a series of first processing segments to perform a plurality of first sub-operations involved in initial processing of packets received from source devices to be buffered in the memory structure; pipelining packets through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission; and pipelining packets through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising:
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a first data pipeline, the first data pipeline used to couple a media access control (MAC) interface to facilitate receipt and transmission packets over a physical interface, a receive packet processor configured to perform initial processing of received packets that are buffered in a first memory, and a backplane manager configured to compute an appropriate destination and dispatch packets on the backplane; and a second data pipeline, the second data pipeline used to couple a transmission accumulator configured to receive packets from the backplane and organize the packets for transmission that are buffered in a second memory, a transmit packet processor configured to schedule the transmission of packets, and the MAC interface. - View Dependent Claims (10, 11, 12)
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14. A method for switching data between one or more source devices and one or more destination devices, the method comprising:
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pipelining data between a media access control (MAC) interface, a receive packet processor coupled to the MAC interface and a first memory, the receive packet processor configured to perform initial processing of received packets to be buffered in the first memory, and a backplane manager coupled to the first memory and a backplane, the backplane manager configured compute an appropriate destination and dispatch packets to the backplane; and pipelining data between a transmission accumulator coupled to the backplane and a second memory, the transmission accumulator configured to organize packets received from the backplane for transmission to the second memory, and a transmit packet processor coupled to the second memory and the MAC interface, the transmit packet processor configured to schedule the transmission of packets to the MAC interface.
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15. A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure, the processors being programmed or wired to pipeline packets for switching packets rapidly between one or more source devices and one or more destination devices, the device comprising:
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a first series of processing segments for pipelining packets through a plurality of first sub-operations involved in initial processing of packets received from source devices to be buffered in the memory structure; a second series of processing segments for pipelining packets through a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission; and a third series of processing segments for pipelining packets through a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices. - View Dependent Claims (13, 16, 17, 18, 19, 20, 21)
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Specification