METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY

• US 20090280607A1
• Filed: 05/09/2008
• Published: 11/12/2009
• Est. Priority Date: 05/09/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chatty, Kiran V., Abadeer, Wagdi W., Tonti, William R., Gauthier, Robert J. JR., Rankin, Jed H., Shi, Yun
• Granted Patent: US 7,700,428 B2
• Time in Patent Office: Days
• US Class Current: 438/211
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

Claims

1. A method for forming a non-volatile random access memory on an insulating layer, the method comprising:

forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship;

doping the first semiconductor body to form a source and a drain separated by a channel;

partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body;

forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode;

forming a second dielectric layer on a top surface of the floating gate electrode; and

forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

2. The method of claim 1 wherein the first semiconductor body includes a first sidewall and the second semiconductor body includes a second sidewall that confronts the first sidewall, and forming the first dielectric layer further comprises:

growing a first silicon dioxide layer on the first sidewall of the first semiconductor body; and

growing a second silicon dioxide on the second sidewall of the second semiconductor body.

3. The method of claim 2 wherein the first and second silicon dioxide layers are separated by a gap, and forming the first dielectric layer further comprises:

depositing a fill layer of a dielectric material to fill between the first and second silicon dioxide layers.

4. The method of claim 1 wherein the first and second semiconductor bodies are concurrently formed from a single crystal silicon layer carried on the insulating layer, and forming the first and second semiconductor bodies further comprises:

forming a hard mask on the single crystal silicon layer;

patterning the hard mask with masked regions that are complimentary to the first and second semiconductor bodies; and

removing unmasked portions of the single crystal silicon layer to form the first and second semiconductor bodies.

5. The method of claim 1 wherein partially removing the second semiconductor body further comprises:

partially masking the second semiconductor body with a dielectric cap; and

removing unmasked end portions of the second semiconductor body with an etching process that removes the unmasked end portions selective to the dielectric cap to define the floating gate electrode.

6. The method of claim 5 further comprising:

forming a photoresist mask on the first semiconductor body to protect the first semiconductor body against the etching process when the unmasked end portions of the second semiconductor body are removed.

7. The method of claim 1 further comprising:

depositing another insulating layer that covers the top surface of the floating gate electrode;

depositing a conductor layer on the insulating layer covering the top surface of the floating gate electrode; and

patterning the conductor layer and the insulating layer covering the top surface of the floating gate electrode to respectively define the control gate electrode and the second dielectric layer.