METHODS OF FABRICATING INTERCONNECT STRUCTURES CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS

• US 20090280636A1
• Filed: 05/09/2008
• Published: 11/12/2009
• Est. Priority Date: 05/09/2008
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Chih-Chao, Hsu, Louis L., Tonti, William R.
• Granted Patent: US 8,772,156 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Claims

1. A method comprising:

forming a first interconnect structure having a first interfacial structure; and

forming a second interconnect structure adjacent to the first structure and having a second interfacial structure different from the first interfacial structure.

2. The method of claim 1, wherein the first interconnect structure is a wiring interconnect structure and the second interconnect structure is an e-fuse.

3. The method of claim 2, wherein the first interfacial structure is formed with a metal layer and a capping layer comprising SiN and the second interfacial structure is formed with a metal layer in a same process as the metal layer of the first interfacial structure and a capping layer comprising one of:

Co(W,P,B), Ru, Ir, Rh and Pt.

4. The method of claim 2, wherein the first interfacial structure is formed with a same material as the second interfacial structure and further comprising degrading interfacial properties between a metal layer and capping layer of the second interfacial structure.

5. The method of claim 4, wherein the degrading includes a damaging treatment from one of radiation sources and laser light.

6. The method of claim 2, wherein the first interfacial structure has a greater electromigration (EM) resistance than the second interfacial structure.

7. The method of claim 1, further comprising forming a third interconnect structure having a third interfacial structure, different from the first and second interfacial structures.

8. The method of claim 1, wherein the second interfacial structure is formed with a capping layer different from a capping layer of the first interfacial structure.

9. The method of claim 1, wherein:

forming the first interconnect structure and the second interconnect structure includes forming in a same processing flow a first wiring layer in a first dielectric, forming a second wiring layer in a second dielectric, forming an electrical interconnect between the first wring layer and the second wiring layer, and forming a capping layer over the second wiring layer through a deposition process; and

forming the second interconnect structure further includes one of;

(i) damaging the capping layer or upper second wiring layer on the second interconnect structure in certain areas/macros and (ii) etching away at least portions of the capping layer over the second wiring layer and depositing another capping material over the second wiring layer in certain areas/macros.

10. The method of claim 9, wherein the another capping material or the damaged capping layer provides a different EM resistance than the capping layer of the first interconnect structure.

11. A method comprising:

forming a wiring interconnect structure and an electronic fuse interconnect structure by a same process flow which comprises;

depositing a first wiring layer in a trench of a first dielectric;

depositing a second wiring layer in a trench in a second dielectric;

forming an interconnection which electrically connects the first wiring layer and the second wiring layer; and

depositing a capping material over the second wiring layer, and

wherein one of the capping material and the second wiring layer of the electronic fuse interconnect structure undergoes a process which changes its interfacial properties while protecting the capping material over the wiring interconnect structure.

12. The method of claim 11, wherein the capping layer comprises SiN.

13. The method of claim 11, wherein the undergoing the process of the electronic fuse interconnect structure comprises:

etching the capping layer at least over the second wiring layer to remove the capping layer, while the capping layer of the wiring interconnect structure is protected, and

depositing a material over the second wiring layer that provides a different interfacial property than the SiN deposited over the wiring interconnect structure.

14. The method of claim 13, wherein the material that provides a different interfacial property is one of:

Co(W,P,B), Ru, Ir, Rh and Pt.

15. The method of claim 11, wherein the undergoing the process of the electronic fuse interconnect structure comprises a treatment from one of radiation sources and laser light.

16. The method of claim 11, further comprising forming a second electronic fuse interconnect using the same process flow, wherein the capping layer of the second electronic fuse interconnect undergoes further processing such that an interfacial property of the second electronic fuse is different from a first and second interfacial property of the wiring interconnect structure and an electronic fuse interconnect structure.

17. A method comprising:

forming a first macro having a metal wiring layer on a first level electrically connected to a metal wiring layer on a second layer and a capping layer over the metal wiring layer on the second layer which has a first electromigration (EM) resistance; and

forming a second macro adjacent the first macro, the second macro being formed with a metal wiring layer on the first level electrically connected to a metal wiring layer on the second layer with a same process flow of the first macro, and additionally forming a capping layer over the metal wiring layer on the second layer which has a second electromigration (EM) resistance different from the first electromigration (EM) resistance.

18. The method of claim 17, wherein the capping layer of the first macro is SiN and the capping layer of the second macro is one of Co(W,P,B), Ru, Ir, Rh and Pt.

19. The method of claim 17, wherein the capping layer of the first and the second macro is a same material, and the capping layer on the second macro and/or the metal wiring layer on the second layer of the second macro is damaged thereby providing a different electromigration (EM) resistance than that of the first macro.

20. A method of forming an interconnect structure comprising:

forming a first macro having a first e-fuse programmability comprising an upper wiring layer capped by a capping material; and

forming a second macro having a second e-fuse programmability comprising an upper wiring layer formed in the same processing step as the first macro and capping the second macro having interfacial properties different than that of the first macro.

21. The method of claim 20, wherein the capping of the second macro includes a same material as the first macro and further includes damaging the material or the upper wiring layer of the second macro.

22. The method of claim 20, wherein the capping of the second macro includes a same material as the first macro and further comprising etching of the same material on the second macro to remove the same material and depositing another type of material.