ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES
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Abstract
Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
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Citations
45 Claims
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1-26. -26. (canceled)
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27. An error detection circuit implemented on a logic device, comprising:
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a multiplexer that takes as input an expected value and configuration data stored on the logic device; and check circuitry coupled to an output of the multiplexer that includes; an XOR tree to implement a polynomial checksum computation, a signature register coupled to the XOR tree, and a logic gate coupled to the signature register, wherein the logic gate takes, as a bit-wise input, content of the signature register. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45-81. -81. (canceled)
Specification