Transistors, semiconductor devices and methods of manufacturing the same

• US 20090283763A1
• Filed: 05/14/2009
• Published: 11/19/2009
• Est. Priority Date: 05/15/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jaechul, Kwon, Keewon
• Granted Patent: US 8,384,076 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor having a self-align top gate structure and methods of manufacturing the same are provided. The transistor includes an oxide semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The transistor further includes a gate insulating layer and a gate electrode, which are sequentially stacked on the channel region. Semiconductor devices including at least one transistor and methods of manufacturing the same are also provided.

Claims

1. A transistor comprising:

an oxide semiconductor layer formed on a substrate, the oxide semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; and

a stack structure including a gate insulating layer and a gate electrode, which are stacked on the channel region.

2. The transistor of claim 1, wherein the source region and the drain region are plasma-treated.

3. The transistor of claim 1, wherein each of the source region and the drain region includes,

at least two regions having different conductivities, wherein

a first of the at least two regions is adjacent to the channel region and has a smaller conductivity than a second of the at least two regions.

4. The transistor of claim 3, further comprising:

an insulating spacer formed at each side wall of the stack structure, wherein

each of the first regions is arranged below a corresponding insulating spacer.

5. The transistor of claim 1, further comprising:

a bottom gate electrode disposed below the channel region.

6. The transistor of claim 1, wherein the oxide semiconductor layer has a multi-layer structure including at least two layers stacked sequentially.

7. The transistor of claim 6, wherein a first of the at least two layers is a ZnO-based oxide layer.

8. The transistor of claim 6, wherein a second of the at least two layers includes,

at least one of IZO, ITO, AZO, GZO, a combination thereof, or an oxide having an electrical conductivity greater than that of the first of the at least two layers.

9. A semiconductor device comprising:

a first transistor including,

a first oxide semiconductor layer formed on a substrate, the first oxide semiconductor layer having a first source region, a first drain region, and a first channel region between the first source region and the first drain region, and

a first stack structure including a first gate insulating layer and a first gate electrode, which are stacked on the first channel region; and

a second transistor including,

a second oxide semiconductor layer having a second source region, a second drain region, and a second channel region between the second source region and the second drain region, and

a second stack structure including a second gate insulating layer and a second gate electrode, which are stacked on the second channel region.

10. The semiconductor device of claim 9, wherein the second oxide semiconductor layer has a type that is the same as or different from the first oxide semiconductor layer.

11. The semiconductor device of claim 10, wherein when the second oxide semiconductor layer is a different type from the first oxide semiconductor layer, an insulating layer is arranged between the substrate and the second transistor, and the first and second oxide semiconductor layers are arranged on different layers.

12. The semiconductor device of claim 9, further comprising:

a bottom gate electrode arranged below at least one of the first channel region and the second channel region.

13. The semiconductor device of claim 9, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a multi-layer structure including at least two layers stacked sequentially.

14. The semiconductor device of claim 13, wherein a first of the at least two layers is a ZnO-based oxide layer.

15. The semiconductor device of claim 13, wherein a second of the at least two layers includes at least one of IZO, ITO, AZO, GZO, a combination thereof, or an oxide having greater electrical conductivity than that of the first of the at least two layers.

16. The semiconductor device of claim 9, wherein the first source region, the first drain region, the second source region and the second drain region are plasma-treated.

17. A method of manufacturing a transistor comprising:

forming an oxide semiconductor layer on a region of a substrate;

forming a stack structure including a gate insulating layer and a gate electrode, which are stacked on the oxide semiconductor layer; and

forming a source region and a drain region in portions of the oxide semiconductor layer, which are disposed on both sides of the stack structure.

18. The method of claim 17, wherein the forming of the source region and the drain region includes,

first plasma-treating portions of the oxide semiconductor layer at each side of the stack structure to form conductive regions at each side of the stack structure.

19. The method of claim 18, further including,

forming insulating spacers at each side wall of the stack structure;

and

second plasma-treating the oxide semiconductor layer at each side of the stack structure and the insulating spacers.

20. The method of claim 17, further comprising:

forming a bottom gate electrode on the substrate; and

forming a lower insulating layer covering the bottom gate electrode;

wherein

the oxide semiconductor layer is formed on the lower insulating layer formed on the bottom gate electrode.

21. The method of claim 17, wherein the oxide semiconductor layer is formed as a multi-layer structure including at least two layers stacked sequentially.

22. The method of claim 21, wherein a first of the at least two layers is a ZnO-based oxide.

23. The method of claim 21, wherein a second of the at least two layers includes at least one of IZO, ITO, AZO, GZO, a combination thereof, or an oxide having greater electrical conductivity than that of the first of the at least two layers.

24. A method of manufacturing a semiconductor device including at least two transistors, the method comprising:

forming a first transistor which includes,

forming a first oxide semiconductor layer on a first region of a substrate;

forming a first stack structure including a first gate insulating layer and a first gate electrode, which are stacked on the first oxide semiconductor layer; and

forming a first source region and a first drain region in portions of the first oxide semiconductor layer, which are disposed on both sides of the first stack structure; and

forming a second transistor which includes,

forming a second oxide semiconductor layer on a second region of the substrate;

forming a second stack structure including a second gate insulating layer and a second gate electrode, which are stacked on the second oxide semiconductor layer; and

forming a second source region and a second drain region in portions of the second oxide semiconductor layer, which are disposed on both sides of the second stack structure.

25. The method of claim 24, wherein the first and second oxide semiconductor layers are different types, and the forming of the first stack structure includes,

forming a first gate insulating material layer covering the first oxide semiconductor layer,

forming an etch-stop layer on the first gate insulating material layer,

forming the second oxide semiconductor layer on the etch-stop layer of the second region of the substrate,

forming a second gate insulating material layer covering the second oxide semiconductor layer on the etch-stop layer,

sequentially removing the second gate insulating material layer and the etch-stop layer from the first region,

forming a first gate electrode material layer on the first gate insulating material layer, and

patterning the first gate electrode material layer and the first gate insulating material layer, wherein

the first gate electrode material layer is formed on the first gate insulating material layer of the first region and the second gate insulating material layer of the second region, and

the first gate electrode material layer and the second gate insulating material layer of the second region are patterned to form the second stack structure on the second oxide semiconductor layer.

26. The method of claim 24, wherein the first and second oxide semiconductor layers are the same type, and the first and second oxide semiconductor layers are formed on the same layer.

27. The method of claim 24, further comprising:

forming a bottom gate electrode below at least one of the first and second oxide semiconductor layers.

28. The method of claim 24, wherein the at least one of the first and second semiconductor layers are formed as a multi-layer structure including at least two layers.

29. A transistor comprising:

a source region and a drain region formed on a substrate;

a channel region formed on the substrate between the source region and the drain region, the channel region being formed of an oxide semiconductor; and

a stack structure including a gate insulating layer and a gate electrode stacked on the channel region;

wherein

the source and drain regions do not overlap the gate electrode.

30. The transistor of claim 29, wherein the source and drain regions are formed of an oxide semiconductor.

31. The transistor of claim 29, wherein each of the source and drain regions have an Indium-rich surface region.

32. The transistor of claim 31, wherein each of the source and drain regions are formed of an oxide semiconductor.

33. The transistor of claim 29, wherein each of the source and drain regions have a plasma-treated surface region.

34. The transistor of claim 33, wherein each of the source and drain regions are formed of an oxide semiconductor.

35. A transistor comprising:

a source region and a drain region formed on a substrate, each of the source and drain regions being formed of an oxide semiconductor and having an Indium-rich surface region;

a channel region formed on the substrate between the source region and the drain region; and

a stack structure formed on the channel region, the stack structure including a gate insulating layer and a gate electrode stacked sequentially.

36. The transistor of claim 35, wherein the Indium-rich surface regions of the source and drain regions are plasma-treated.

37. The transistor of claim 36, wherein the channel region is formed of an oxide semiconductor.

38. The transistor of claim 37, wherein each of the source and drain regions are plasma-treated.

39. A transistor comprising:

a source region and a drain region formed on a substrate, each of the source and drain regions being formed of an oxide semiconductor and having a plasma-treated surface region;

a channel region formed on the substrate between the source region and the drain region; and

a stack structure including a gate insulating layer and a gate electrode stacked on the channel region.

40. The transistor of claim 39, wherein the channel region is formed of an oxide semiconductor.

41. The transistor of claim 40, wherein each of the source and drain regions have an Indium-rich surface region.

42. The transistor of claim 41, wherein the source and drain regions do not overlap the gate electrode.