SEMICONDUCTOR DEVICE

• US 20090283797A1
• Filed: 10/01/2008
• Published: 11/19/2009
• Est. Priority Date: 05/13/2008
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Tomomatsu, Yoshifumi, TAKAHASHI, Tetsuo
• Granted Patent: US 8,178,947 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 μm.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces;

a first impurity region of a first conductivity type, formed between said first main surface and said second main surface;

a second impurity region of a second conductivity type, formed at said second main surface;

a first groove portion formed at said first main surface and reaching said first impurity region;

a first electrode formed in said first groove portion with a first insulating film interposed therebetween;

a second groove portion formed apart from said first groove portion and reaching said first impurity region from said first main surface;

a second electrode formed in said second groove portion with a second insulating film interposed therebetween;

a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode;

a third impurity region of said first conductivity type, formed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode;

a fourth impurity region of the second conductivity type, formed at said first main surface located between said first electrode and said second electrode, and formed to surround said third impurity region;

a main electrode formed on said first main surface and connected to said third impurity region and said fourth impurity region;

an interlayer insulating film formed on said first electrode and capable of insulating said main electrode and said first electrode from each other; and

a fifth impurity region of the first conductivity type, formed between said first and second electrodes and between said fourth impurity region and said first impurity region, and having impurity concentration higher than impurity concentration of said first impurity region, and

a width of said fifth impurity region in a direction along which said first electrode and said second electrode are aligned being set to be at most 1.4 μ

m.

2. The semiconductor device according to claim 1, wherein the width of said fifth impurity region is set to be at most 1.2 μ

m.

3. The semiconductor device according to claim 1, further comprising a sixth impurity region of said second conductivity type, formed at said first main surface adjacent to said second electrode on a side opposite to said fourth impurity region with respect to said second electrode, wherein

said main electrode extends in the direction along which said first and second electrodes are aligned, and is connected to said second electrode, and

said interlayer insulating film is formed on said sixth impurity region to insulate said sixth impurity region and said main electrode from each other.

4. The semiconductor device according to claim 3, further comprising a third groove portion formed in said sixth impurity region and formed to split said sixth impurity region, and a third electrode formed in said third groove portion with a third insulating film interposed therebetween, wherein said third electrode is connected to said main electrode.

5. The semiconductor device according to claim 4, wherein a depth of said third electrode is larger than a depth of said second electrode.

6. The semiconductor device according to claim 4, wherein a width of said third electrode is larger than a width of said second electrode.

7. The semiconductor device according to claim 1, further comprising

a fourth groove portion formed apart from said second groove portion,

a fourth electrode formed in said fourth groove portion with a fourth insulating film interposed therebetween,

a fifth groove portion provided apart from said fourth groove portion on a side opposite to said second groove portion with respect to said fourth groove portion, and

a fifth electrode formed in said fifth groove portion with a fifth insulating film interposed therebetween, wherein

said second electrode is connected to said gate wiring, and

said fifth electrode is connected to said gate wiring, and said fourth electrode is connected to said main electrode.

8. The semiconductor device according to claim 7, further comprising a sixth impurity region formed on a main surface of said semiconductor substrate located between said second electrode and the fourth electrode, and on the main surface of said semiconductor substrate located between said fourth electrode and the fifth electrode, and electrically separated from said main electrode by said interlayer insulating film.

9. The semiconductor device according to claim 8, wherein

a plurality of said fourth electrodes are formed apart from one another, on the main surface of said semiconductor substrate located between said second electrode and said fifth electrode, and

said sixth impurity region is formed on the main surface of said semiconductor substrate located between said fourth electrodes.

10. The semiconductor device according to claim 9, wherein a spacing between said fourth electrode and said second electrode is made to be smaller than a spacing between said fourth electrodes.

11. The semiconductor device according to claim 7, wherein a width of said fourth electrode is made to be larger than a width of each of said first and second electrodes.

12. The semiconductor device according to claim 7, wherein a depth of said fourth electrode is made to be larger than a depth of each of said first and second electrodes.