System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack

• US 20090283871A1
• Filed: 07/23/2008
• Published: 11/19/2009
• Est. Priority Date: 05/14/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Hung-Pin, Chiou, Wen-Chih, Wu, Weng-Jin
• Granted Patent: US 8,853,830 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Claims

1. An integrated circuit comprising:

a substrate having an active region formed therein;

a via extending through the substrate, having a first termination substantially aligned with a bottom surface of the substrate and a second termination substantially aligned to a top surface of the substrate;

a first conductive contact electrically connected to the second termination of the via and electrically connected to a conductive interconnect layer; and

a second conductive contact electrically connected to the conductive interconnect layer and the active region.

2. The integrated circuit of claim 1 further comprising a liner material substantially surrounding the via and wherein the liner does not surround the first conductive contact.

3. The integrated circuit of claim 2, wherein the liner material comprises a dielectric material.

4. The integrated circuit of claim 1, wherein the top surface of the substrate is a top surface of a semiconductor material.

5. The integrated circuit of claim 1 further comprising a first bonding joint connected to the first termination of the via.

6. The integrated circuit of claim 1 further comprising a second substrate wherein the second substrate has a second bonding joint connected to the substrate.

7. The integrated circuit of claim 6, wherein the first and second bonding joints are physically contacting.

8. The integrated circuit of claim 6 further comprising:

a contacting area_cc of the first conductive contact; and

a contacting area_via of the via, wherein contacting area_cc is less than contacting area_via.

9. The integrated circuit of claim 6, wherein a plurality of the first conductive contacts contact a single via.

10. The integrated circuit of claim 6, wherein a material of the first conductive contact is selected from the group consisting of Cu, W, alloy, or other conducting material.

11. A semiconductor substrate structure, the structure comprising:

a backside;

a front-face;

a bulk layer;

an interconnect layer, wherein the interconnect layer includes a plurality of conductive layers sandwiched between inter-metal dielectric layers;

a contact layer, wherein the contact layer is between the bulk layer and the interconnect layer; and

a through substrate via (TSV) commencing between the bulk layer and the contact layer and terminating at the backside of the bulk layer, wherein the TSV is electrically coupled to the interconnect layer, and wherein the TSV is electrically coupled to the backside.

12. The structure of claim 11 further comprising:

a lining, on sidewalls of the TSV.

13. The structure of claim 11, wherein the TSV comprises a metal that is isolated from the bulk layer by the liner, and wherein the liner is limited to the bulk layer.

14. The structure of claim 11 further comprising:

a plurality of contacts, wherein the TSV is electrically coupled to the interconnect layer at least through a first contact, and

a circuit, wherein the circuit is electrically coupled to the interconnect layer at least through a second contact, wherein the first contact and the second contact are formed in the contact layer.

15. The structure of claim 11 further comprising:

a bonding region on the front-face, wherein the interconnect layer is between the bonding region and the TSV.

16. The structure of claim 15 further comprising:

a second substrate with a second bonding region, wherein the bonding region of the semiconductor substrate structure is bonded to the second bonding region of the second substrate.

17. The structure of claim 11, wherein the bulk layer is silicon.

18. A system of stacked semiconductor substrates, the system comprising:

a first substrate including;

a backside;

a front-face;

a bulk layer, wherein the bulk layer comprises a semiconductor material;

a contact layer, wherein the contact layer is between the bulk layer and an interconnect layer;

an interconnect layer, wherein the interconnect layer includes a plurality of inter-metal dielectric layers sandwiched between a plurality of conductive layers;

a lined TSV commencing between the contact layer and terminating at the backside, wherein the lined TSV is electrically coupled to the interconnect layer and wherein the lined TSV is electrically coupled to a bonding pad on the backside; and

a bonding joint, wherein the bonding joint is on the front-face and is electrically connected to the interconnect layer; and

a second substrate bonded to the first substrate at the bonding joint.

19. The system of stacked semiconductor substrates of claim 18, wherein a lining is disposed into the lined TSV prior to any first substrate metal processes.

20. The system of stacked semiconductor substrates of claim 18, wherein a bonding metal at the bonding joint is selected from the group consisting of Cu, W, Au, Sn, Pb and an alloy thereof.

21. A method of manufacturing a stacked substrate structure, the method comprising:

etching a front-face of a first substrate to create a through substrate via (TSV), at a step before contact etch;

forming an at least a first contact between the TSV and an interconnect layer;

forming an at least a second contact between an active region and the interconnect layer;

thinning a backside of the first substrate to expose the TSV;

filling the TSV with a conductive material; and

disposing a backside bonding pad, wherein the backside bonding pad is electrically coupled to the TSV.

22. The method of claim 21, wherein the first substrate is comprised of a semiconductor material.

23. The method of claim 22, wherein the first substrate is comprised of silicon.

24. The method of claim 21, further comprising:

lining the TSV with a dielectric.

25. The method of claim 24, wherein the dielectric is disposed into the TSV prior to any metal processes performed on the first substrate.

26. The method of claim 21 further comprising:

filling the TSV with a sacrificial material, before forming the at least first contact.

27. The method of claim 26, wherein the sacrificial material is selected from the group consisting of a nitride, an oxide, a doped polysilicon or an undoped polysilicon.

28. The method of claim 26 further comprising:

depositing an etch stop layer on the sacrificial material in the TSV, before forming the at least first contact.

29. The method of claim 28, wherein the etch stop layer is selected from the group of materials consisting of Si, Si_xC_y, Si_xN_y, Si_xC_y, Si_xO_y, Si_xO_yN_z.

30. The method of claim 21, wherein the at least first contact, is an array of first contacts contacting a single TSV.

31. The method of claim 28 further comprising:

disposing a hard mask passivation layer on the backside of the first substrate, following thinning the backside;

planarizing the backside of the first substrate to expose the sacrificial material;

removing the sacrificial material; and

removing the etch stop layer prior to filling the TSV with the conductive material.

32. The method of claim 31, wherein an etch selectivity for the etch stop layer is greater than an etch selectivity of the hard mask passivation layer.

33. The method of claim 31, wherein the hard mask passivation layer is comprised of a nitride.

34. The method of claim 31, wherein the planarizing is accomplished by a chemical mechanical polish (CMP) process.

35. The method of claim 21, wherein the conductive material is Cu, Al, and alloys thereof.

36. The method of claim 21 further comprising:

following filling the TSV with the conductive material, disposing a dielectric topping layer on the backside of the first substrate.

37. The method of claim 21 further comprising:

after the forming at least the second contact between the active region and the interconnect layer, electrically coupling a first bonding joint to the interconnect layer; and

physically bonding the first bonding joint to a second bonding joint on a second substrate, before thinning the backside of the first substrate to expose the TSV.