INTEGRATING HIGH STRESS CAP LAYER IN HIGH-K METAL GATE TRANSISTOR

• US 20090283922A1
• Filed: 12/27/2007
• Published: 11/19/2009
• Est. Priority Date: 12/27/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Sandford, Justin S., Golonzka, Oleg
• Application Number:
  US11/965,317
• Publication Number:
  US 20090283922A1
• Time in Patent Office: Days
• US Class Current: 257/788
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

In some embodiments an etchstop layer is deposited over a transistor that has been encapsulated by a high-K film, a silicon nitride is deposited over the deposited etchstop layer, the silicon nitride is removed, and the etchstop layer is removed. Other embodiments are described and claimed.

Claims

1. A method comprising:

depositing a thin metal etchstop layer over a high-K metal gate transistor with a strained channel, wherein the transistor has been encapsulated by a high-K film;

depositing a high stress silicon nitride film encapsulating the gate and transistor body over the deposited etchstop layer, wherein the thin metal etchstop layer is sandwiched between the high-K film and the high stress silicon nitride film;

removing the silicon nitride using a wetetch process that is selective to the etchstop layer; and

removing the etchstop layer using a selective wetetch process.

3. The method of claim 1, wherein the etchstop layer is a tantalum-nitride layer.

4. The method of claim 1, wherein the removing the silicon nitride stops on the etchstop layer.

5. The method of claim 1, wherein the removing the silicon nitride includes using phosphoric acid.

6. The method of claim 1, wherein the removing the silicon nitride includes using HF-based etchant.

7. The method of claim 1, wherein the removing the etchstop layer includes using hydrogen peroxide solution that is selective to high-K.

8. The method of claim 1, wherein the depositing of the etchstop layer is via atomic layer deposition.

9. The method of claim 1, further comprising after depositing the silicon nitride over the deposited etchstop layer and before removing the silicon nitride, subjecting the structure to a rapid high temperature anneal.

21. The method of claim 1, further comprising introducing uniaxial strain in the high-K metal gate transistor channel by applying a sacrificial high stress film in the semiconductor process flow that integrates the film.

22. The method of claim 1, further comprising:

forming source/drain extensions or tips; and

introducing strain to the channel by annealing the gate and transistor body capped with a the silicon nitride film.

2. (canceled)

10. (canceled)

11. (canceled)

12. A product made by the process:

depositing an a thin metal etchstop layer over a high-K metal gate transistor with a strained channel, wherein the transistor that has been encapsulated by a high-K film;

depositing a high stress silicon nitride film encapsulating the gate and transistor body over the deposited etchstop layer, wherein the thin metal etchstop layer is sandwiched between the high-K film and the high stress silicon nitride film;

removing the silicon nitride using a wetetch process that is selective to the etchstop layer; and

removing the etchstop layer using a selective wetetch process.

14. The product of claim 12, wherein the etchstop layer is a tantalum-nitride layer.

15. The product of claim 12, wherein the removing the silicon nitride stops on the etchstop layer.

16. The product of claim 12, wherein the removing the silicon nitride includes using phosphoric acid.

17. The product of claim 12, wherein the removing the silicon nitride includes using HF-based etchant.

18. The product of claim 12, wherein the removing the etchstop layer includes using hydrogen peroxide solution that is selective to high-K.

19. The product of claim 12, wherein the depositing of the etchstop layer is via atomic layer deposition.

20. The product of claim 12, the process further comprising after depositing the silicon nitride over the deposited etchstop layer and before removing the silicon nitride, subjecting the structure to a rapid high temperature anneal.

23. The product of claim 12, wherein the process further includes introducing uniaxial strain in the high-K metal gate transistor channel by applying a sacrificial high stress film in the semiconductor process flow that integrates the film.

24. The product of claim 12, the process further comprising:

forming source/drain extensions or tips; and

introducing strain to the channel by annealing the gate and transistor body capped with a the silicon nitride film.

13. (canceled)