Write Assist Circuit for Improving Write Margins of SRAM Cells

• US 20090285010A1
• Filed: 10/17/2008
• Published: 11/19/2009
• Est. Priority Date: 05/14/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Chung-Ji, Lum, Annie-Li-Keow, Tao, Derek C., Kengeri, Subramani
• Granted Patent: US 7,898,875 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.

Claims

1. A memory circuit comprising:

a memory array comprising;

a plurality of memory cells arranged in rows and columns;

a plurality of first bit-lines, each connected to a column of the memory array; and

a plurality of write-assist latches, each connected to one of the plurality of first bit-lines, wherein each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.

2. The memory circuit of claim 1 further comprising:

a plurality of multiplexers, each connected to a starting end of one of the plurality of first bit-lines; and

a plurality of write drivers, each connected to one of the plurality of multiplexers, wherein each of the plurality of write-assist latches is connected to a terminating end of one of the plurality of first bit-lines.

3. The memory circuit of claim 2 further comprising:

a control block comprising a plurality of Y-decode lines; and

a plurality of assist-enable units, each comprising a first input connected to one of the plurality of Y-decode lines, and an output connected to one of the plurality of write-assist latches, wherein a multiplexer and an assist-enable unit of a same column are controlled by a same Y-decode line.

4. The memory circuit of claim 3, wherein each of the plurality of assist-enable units is configured to delay a period of time to sync with a voltage on a connecting one of the plurality of first bit-lines.

5. The memory circuit of claim 3, wherein the memory array further comprises a write enable line, and wherein each of the plurality of assist-enable units further comprises a second input connected to the write enable line.

6. The memory circuit of claim 1, wherein the memory array comprises:

a plurality of segments, wherein the plurality of write-assist latches is in a same row in one of the plurality of segments; and

a control block comprising a plurality of local control signal lines, wherein the plurality of write-assist latches is connected to a same one of the plurality of local control signal lines.

7. The memory circuit of claim 6 further comprising a plurality of rows of write-assist latches, each row being connected to a same one of the plurality of local control signal lines, wherein each of the plurality of segments comprises one row of the plurality of rows of write-assist latches.

8. The memory circuit of claim 1 further comprising a plurality of second bit-lines, each forming a differential pair with, and in a same column as, one of the plurality of first bit-lines.

9. A memory circuit comprising:

a control block comprising a plurality of Y-decode outputs;

a write enable line;

a memory array comprising a plurality of memory cells arranged in rows and columns, wherein the columns comprise a first column and a second column;

a first bit-line connected to the first column;

a multiplexer connected to a starting end of the first bit-line, wherein the multiplexer is further connected to a first Y-decode output in the plurality of Y-decode outputs through a first Y-decode signal line;

a write driver connected to the multiplexer;

a first write-assist latch connected substantially close to a terminating end of the first bit-line; and

a first assist-enable unit comprising a first input connected to the first Y-decode signal line, a second input connected to the write enable line, and an output connected to the first write-assist latch, wherein the first write-assist latch is configured to be enabled and disabled by the output of the first assist-enable unit.

10. The memory circuit of claim 9 further comprising a second bit-line forming a differential pair with the first bit-line, wherein the second bit-line is connected to the first write-assist latch.

11. The memory circuit of claim 9, wherein the first assist-enable unit is configured to provide an assist-enable signal for turning on the first write-assist latch, and to sync the assist-enable signal with a voltage on the first bit-line.

12. The memory circuit of claim 9, wherein the first assist-enable unit is configured to provide an assist-enable signal for turning on the first write-assist latch when both the first Y-decode signal line and the write enable line are at on states.

13. The memory circuit of claim 9, wherein the first write-assist latch is configured to increase a voltage on the terminating end of the first bit-line to substantially equal to a voltage on the starting end of the first bit-line.

14. The memory circuit of claim 9 further comprising:

a second bit-line connected to the second column;

a second write-assist latch connected substantially close to a terminating end of the second bit-line; and

a second assist-enable unit comprising a first input connected to a second Y-decode signal line, a second input connected to the write enable line, and an output connected to the second write-assist latch, wherein the second Y-decode signal line is connected to a second Y-decode output in the plurality of Y-decode outputs.

15. The memory circuit of claim 14, wherein the first and the second assist-enable units are configured to turned on the first and the second write-assist latches independently.

16. The memory circuit of claim 14, wherein the first and the second columns comprise memory cells in a same word, and wherein the first and the second assist-enable units are configured to turned on the first and the second write-assist latches simultaneously.

17. The memory circuit of claim 14, wherein the first assist-enable unit is disconnected from the second Y-decode signal line, and wherein the second assist-enable unit is disconnected from the first Y-decode signal line.

18. A memory circuit comprising:

a control block comprising a plurality of local control signal lines;

a memory array comprising a plurality of memory cells arranged in rows and columns; and

a row of write-assist latches, each connected to one column of the memory cells, wherein the row of write-assist latches is connected to one of the plurality of local control signal lines.

19. The memory circuit of claim 18, wherein the rows of the memory array are configured as a plurality of segments, and wherein the row of write-assist latches is in substantially a middle position of the one of the segments.

20. The memory circuit of claim 19 further comprising additional rows of write-assist latches, wherein each of the additional rows is in one of the plurality of segments.

21. A method of operating a memory circuit, the method comprising:

providing a control block comprising a plurality of Y-decode signal lines;

providing a memory array comprising;

a column;

a bit-line connected to the column;

a multiplexer connected to a starting end of the bit-line; and

a first write-assist latch connected to the bit-line; and

during a writing time of a memory cell in the column, turning on the first write-assist latch to increase a voltage on the bit-line.

22. The method of claim 21, wherein the step of turning on the first write-assist latch comprises:

generating a Y-decode signal using the control block;

combining the Y-decode signal and a write enable signal to generate an assist-enable signal; and

applying the assist-enable signal to turn on the first write-assist latch.

23. The method of claim 22 further comprising delaying applying the assist-enable signal until a voltage on the bit-line reaches a threshold value.

24. The method of claim 21, wherein each column of the memory array is connected with one write-assist latch, wherein at the time the write-assist latch is turned on, an additional write-assist latch in a neighboring column is turned off, and wherein the neighboring column comprises no memory cells to be written into.

25. The method of claim 24, wherein at the time the write-assist latch is turned on, all write-assist latches in the memory array and connected to columns comprising no memory cells to be written into are turned off.

26. The method of claim 21, wherein the step of turning on the first write-assist latch comprises:

generating a local control signal using the control block;

using the local control signal to generate an assist-enable signal; and

applying the assist-enable signal to turn on the first write-assist latch.

27. The method of claim 26, wherein the local control signal turns on a row of write-assist latches simultaneously, each in a column of the memory array.

28. The method of claim 26, wherein the memory array comprises a plurality of segments, each connected to a local control signal line of the control block, and wherein the method further comprises:

for writing a memory cell in a segment of the memory array, turning on only write-assist latches in the segment, and turning off all write-assist latches in segments comprising no memory cells to be written into.

29. A method of operating a memory circuit, the method comprising:

providing a control block comprising a plurality of Y-decode signal lines;

providing a memory array comprising;

a first column;

a first differential pair of bit-lines connected to the first column;

a multiplexer connected to a starting end of the first differential pair of bit-lines; and

a first write-assist latch connected substantially close to a terminating end of the first differential pair of bit-lines; and

during a writing time for a memory cell in the first column, turning on the first write-assist latch to increase a voltage on one of the differential pair of bit-lines.

30. The method of claim 29, wherein the step of turning on the first write-assist latch comprises:

generating a first assist-enable signal using a Y-decode signal and a write enable signal, wherein the first assist-enable signal is used for controlling the first column; and

using the first assist-enable signal to turn on the first write-assist latch.

31. The method of claim 30 further comprising delaying the first assist-enable signal until voltages on the first differential pair of bit-lines reaches threshold values before the assist-enable signal is provided to the first write-assist latch.

32. The method of claim 29, wherein the memory array further comprises:

a second column comprising no memory cells for being written into during the writing time;

a second differential pair of bit-lines connected to the second column; and

a second write-assist latch connected substantially close to a terminating end of the second differential pair of bit-lines, wherein the method further comprises, during the writing time, turning off the second write-assist latch.

33. The method of claim 32, wherein the step of turning off the second write-assist latch comprises:

generating a second assist-disable signal using an additional Y-decode signal and a write enable signal, wherein the second assist-disable signal is used for controlling the second column; and

using the second assist-disable signal to turn off the second write-assist latch.

34. A method of operating a memory circuit, the method comprising:

providing a control block comprising a plurality of local control signal lines;

providing a memory array comprising;

a first segment;

a first row of write-assist latches in the first segment;

a plurality of differential pairs of bit-lines, each pair being in a column of the array, wherein each pair is connected to one write-assist latch in the first row;

a second segment; and

a second row of write-assist latches in the second segment and connected to the plurality of differential pairs of bit-lines, wherein each pair of the plurality of differential pairs of bit-lines is connected to one write-assist latch in the second row; and

during a writing time for a memory cell in the first segment, turning on the first row of write-assist latches.

35. The method of claim 34, wherein the memory circuit further comprises a control block configured to provide X-decode and Y-decode signals and local control signals, wherein the step of turning on the first row of write-assist latches comprises inputting one of the local control signals corresponding to the first segment of the first row of write-assist latches.

36. The method of claim 34, wherein during the writing time, the second segment comprises no memory cells to be written into, and wherein the method further comprises turning off the second row of write-assist latches during the writing time.

37. The method of claim 36, wherein the memory circuit further comprises a control block configured to provide X-decode and Y-decode signals and local control signals, wherein the step of turning off the second row of write-assist latches comprises inputting one of the local control signals corresponding to the second segment of the second row of write-assist latches.