Write Assist Circuit for Improving Write Margins of SRAM Cells
First Claim
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1. A memory circuit comprising:
- a memory array comprising;
a plurality of memory cells arranged in rows and columns;
a plurality of first bit-lines, each connected to a column of the memory array; and
a plurality of write-assist latches, each connected to one of the plurality of first bit-lines, wherein each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.
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Abstract
A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.
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Citations
37 Claims
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1. A memory circuit comprising:
a memory array comprising; a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines, wherein each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory circuit comprising:
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a control block comprising a plurality of Y-decode outputs; a write enable line; a memory array comprising a plurality of memory cells arranged in rows and columns, wherein the columns comprise a first column and a second column; a first bit-line connected to the first column; a multiplexer connected to a starting end of the first bit-line, wherein the multiplexer is further connected to a first Y-decode output in the plurality of Y-decode outputs through a first Y-decode signal line; a write driver connected to the multiplexer; a first write-assist latch connected substantially close to a terminating end of the first bit-line; and a first assist-enable unit comprising a first input connected to the first Y-decode signal line, a second input connected to the write enable line, and an output connected to the first write-assist latch, wherein the first write-assist latch is configured to be enabled and disabled by the output of the first assist-enable unit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory circuit comprising:
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a control block comprising a plurality of local control signal lines; a memory array comprising a plurality of memory cells arranged in rows and columns; and a row of write-assist latches, each connected to one column of the memory cells, wherein the row of write-assist latches is connected to one of the plurality of local control signal lines. - View Dependent Claims (19, 20)
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21. A method of operating a memory circuit, the method comprising:
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providing a control block comprising a plurality of Y-decode signal lines; providing a memory array comprising; a column; a bit-line connected to the column; a multiplexer connected to a starting end of the bit-line; and a first write-assist latch connected to the bit-line; and during a writing time of a memory cell in the column, turning on the first write-assist latch to increase a voltage on the bit-line. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A method of operating a memory circuit, the method comprising:
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providing a control block comprising a plurality of Y-decode signal lines; providing a memory array comprising; a first column; a first differential pair of bit-lines connected to the first column; a multiplexer connected to a starting end of the first differential pair of bit-lines; and a first write-assist latch connected substantially close to a terminating end of the first differential pair of bit-lines; and during a writing time for a memory cell in the first column, turning on the first write-assist latch to increase a voltage on one of the differential pair of bit-lines. - View Dependent Claims (30, 31, 32, 33)
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34. A method of operating a memory circuit, the method comprising:
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providing a control block comprising a plurality of local control signal lines; providing a memory array comprising; a first segment; a first row of write-assist latches in the first segment; a plurality of differential pairs of bit-lines, each pair being in a column of the array, wherein each pair is connected to one write-assist latch in the first row; a second segment; and a second row of write-assist latches in the second segment and connected to the plurality of differential pairs of bit-lines, wherein each pair of the plurality of differential pairs of bit-lines is connected to one write-assist latch in the second row; and during a writing time for a memory cell in the first segment, turning on the first row of write-assist latches. - View Dependent Claims (35, 36, 37)
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Specification