SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
First Claim
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1. A sub-system, comprising:
- an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
wherein the at least one aspect is selected from the group consisting of a signal, a capacity, a timing, and a logical interface.
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Abstract
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
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Citations
20 Claims
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1. A sub-system, comprising:
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an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits; wherein the at least one aspect is selected from the group consisting of a signal, a capacity, a timing, and a logical interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method, comprising:
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interfacing a plurality of memory circuits and a system; and simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits; wherein the at least one aspect is selected from the group consisting of a signal, a capacity, a timing, and a logical interface.
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20. A sub-system, comprising:
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an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits; wherein the interface circuit interfaces a majority of address or control signals of the memory circuits.
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Specification