VERIFICATION OF THE INTEGRITY OF A CIPHERING KEY

• US 20090285398A1
• Filed: 05/14/2009
• Published: 11/19/2009
• Est. Priority Date: 05/16/2008
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Teglia, Yannick, Liardet, Pierre-Yvan
• Granted Patent: US 8,848,917 B2
• Time in Patent Office: Days
• US Class Current: 380/277
• CPC Class Codes: G06F 16/00 Information retrieval; Database structures therefor; File system structures therefor
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: H04K 1/00 Secret communication
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 63/12 Applying verification of the received information cryptographic mechanisms or cryptographic arrangements for data integrity or data verification H04L9/32
• CPC Class Codes: H04L 63/123 received data contents, e.g. message integrity
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
• CPC Class Codes: H04L 9/08 Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords network architectures or network communication protocols for supporting key management in a packet data network H04L63/06
• CPC Class Codes: H04L 9/32 including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials

Abstract

A method for verifying the integrity of a key implemented in a symmetrical ciphering or deciphering algorithm, including the steps of complementing to one at least the key; and verifying the coherence between two executions of the algorithm, respectively with the key and with the key complemented to one.

Claims

1. A method for verifying the integrity of a key used in a symmetrical ciphering or deciphering algorithm, comprising the steps of:

complementing to one at least the key; and

verifying the coherence between two executions of the algorithm, respectively with the key and with the key complemented to one.

2. The method of claim 1, wherein the result of a first execution of the algorithm with a data value and the key, or the complement to one of this result, is compared with the complement to one of the result of a second execution of the algorithm with the data value complemented to one and the key complemented to one, respectively with the result of this second execution.

3. The method of claim 1, wherein a first execution of an algorithm of ciphering or deciphering of a data value with the key is followed by an execution of a corresponding deciphering or ciphering algorithm with the complemented result of the first execution and the complemented key.

4. The method of claim 3, wherein the result of the second execution or its complement to one is compared with the complement to one of the data value or with the data value.

5. The method of claim 1, wherein the verification compares two successive executions.

6. The method of claim 1, wherein the verification compares two parallel executions.

7. The method of claim 1, wherein the algorithm used is the DES or one of its variations.

8. An electronic circuit capable of implementing the verification method of claim 1.