SEMICONDUCTOR CHIP HAVING GETTERING LAYER, AND METHOD FOR MANUFACTURING THE SAME

• US 20090286354A1
• Filed: 07/24/2009
• Published: 11/19/2009
• Est. Priority Date: 07/28/2004
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: MATSUKAWA, KAZUHITO, Koga, Tsuyoshi, Shibata, Jun, Tobimatsu, Hiroshi, Nishida, Akio, Higashide, Yoshiko
• Application Number:
  US12/508,775
• Publication Number:
  US 20090286354A1
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Claims

1. A method for manufacturing a semiconductor package, comprising:

forming an element layer on a front face of a semiconductor wafer, the element layer including a transistor;

dicing the semiconductor wafer so as to form a first semiconductor chip, after forming the element layer;

polishing a back face of the first semiconductor chip so as to form a getting layer on the back face, after dicing the semiconductor wafer; and

assembling a semiconductor package which includes a package substrate, a second semiconductor chip formed over the package substrate, the first semiconductor chip being formed over the second semiconductor chip, after polishing the back face of the first semiconductor chip, wherein

the semiconductor package includes the gettering layer,

the gettering layer is a damaged layer;

the damaged layer includes a plurality of grooves,

a thickness of the first semiconductor chip is thinner than a thickness of the second semiconductor chip, and

in plan view to said first semiconductor chip, each of the grooves is a linear groove.

2. The method for manufacturing the semiconductor package according to claim 1, wherein the semiconductor package includes resin and a spacer, the method comprising:

covering the first and second semiconductor chips and a front face of the package substrate with the resin, and

arranging the spacer between the first semiconductor chip and the second semiconductor chip.

3. The method for manufacturing the semiconductor package according to claim 2, wherein:

the spacer is a silicon substrate or a polysilicon film,

a back face of the second semiconductor chip includes a gettering layer, and

the semiconductor package includes a first wire and a second wire, the method comprising;

electrically coupling the first semiconductor chip to the package substrate via the first wire, and

electrically coupling the second semiconductor chip to the package substrate via the second wire.

4. A method for manufacturing a semiconductor package, comprising:

forming an element layer on a front face of a semiconductor wafer, the element layer including a transistor;

dicing the semiconductor wafer so as to form a first semiconductor chip, after forming the element layer;

polishing a back face of the first semiconductor chip so as to form a getting layer on the back face, after dicing the semiconductor wafer; and

assembling a semiconductor package which includes a package substrate, the first semiconductor chip being formed over the package substrate, after polishing the back face of the first semiconductor chip, wherein

the semiconductor package includes the gettering layer,

the gettering layer is a damaged layer,

the damaged layer includes a plurality of grooves,

a depth of each of the grooves is 2 to 3 μ

m, and

in a plan view to said first semiconductor chip, each of the grooves is a linear groove.

5. The method for manufacturing the semiconductor package according to claim 4, comprising covering the first semiconductor chip and a front face of the package substrate with a resin.

6. The method for manufacturing the semiconductor package according to claim 5, wherein the semiconductor package includes a first wire, the method comprising electrically coupling the first semiconductor chip to the package substrate via the first wire.