APPARATUS, SYSTEM, AND METHOD FOR DETECTING AND REPLACING FAILED DATA STORAGE

• US 20090287956A1
• Filed: 05/18/2009
• Published: 11/19/2009
• Est. Priority Date: 05/16/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Flynn, David, Thatcher, Jonathan, Fillingim, Jeremy, Aune, Joshua, Strasser, John, Inskeep, Bill, Vigor, Kevin
• Granted Patent: US 8,195,978 B2
• Time in Patent Office: Days
• US Class Current: 714/6
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

An apparatus, system, and method are disclosed for detecting and replacing failed data storage. A read module reads data from an array of memory devices. The array includes two or more memory devices and one or more extra memory devices storing parity information from the memory devices. An ECC module determines, using an error correcting code (“ECC”), if one or more errors exist in tested data and if the errors are correctable using the ECC. The tested data includes data read by the read module. An isolation module selects a memory device in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with replacement data and available data wherein the tested data includes the available data combined with the replacement data.

Claims

1. An apparatus to detect and replace failed data storage, the apparatus comprising:

a read module that reads data from an array of memory devices, the array comprising two or more memory devices and one or more extra memory devices, the extra memory devices storing parity information from the memory devices;

an ECC module that determines, using an error correcting code (“

ECC”

), if one or more errors exist in tested data and if the errors are correctable using the ECC, the tested data comprising data read by the read module;

an isolation module that

selects a memory device from the array of memory devices in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC; and

replaces data read from the selected memory device with data comprising data generated from the parity data stored on the one or more extra memory devices (“

replacement data”

) and data read from the memory devices that are not selected (“

available data”

),

wherein the tested data further comprises the available data combined with the replacement data.

2. The apparatus of claim 1, wherein the isolation module selects a next memory device for testing in response to the ECC module determining that the available data combined with the replacement data contains errors that not are correctable using the ECC, the next memory device selected from the array of memory devices, the isolation module selecting each of the memory devices for testing until the ECC module determines that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC.

3. The apparatus of claim 1, further comprising a retirement module that, in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC, retires one of the selected memory device and one or more storage regions on the selected memory device based on a retirement policy, the one or more storage regions comprising one or more errors, the storage regions comprising at least a portion of the selected memory device.

4. The apparatus of claim 1, further comprising a memory device reconfiguration module that identifies the memory device that was selected in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC such that data is generated to replace read data from the selected memory device for future operations.

5. The apparatus of claim 1, further comprising a logging module that, in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC, one or more of

logs an identity of the selected memory device;

and

logs memory location data specifying one or more storage regions comprising one or more errors, the region comprising at least a portion of the selected memory device.

6. The apparatus of claim 5, wherein the logging module logs the identity of the selected memory device without logging memory location data comprising a storage region with one or more errors.

7. The apparatus of claim 6, further comprising a storage region testing module that identifies one or more storage regions comprising errors within the selected memory device, and wherein the logging module further logs memory location data comprising the one or more storage regions identified by the storage region testing module.

8. The apparatus of claim 7, wherein the storage region testing module identifies storage regions with one or more errors with subsequent reads by the read module and using the ECC module and the isolation module to determine storage regions with uncorrectable errors that are correctable by combining replacement data with available data.

9. The apparatus of claim 5, wherein the logging module logs one or more storage regions comprising one or more errors and further logs memory location data specifying one or more additional storage regions comprising one or more errors in the selected memory device, in response to subsequent reads by the read module and using the ECC module and the isolation module to determine storage regions with uncorrectable errors that are correctable by combining replacement data with available data.

10. The apparatus of claim 9, wherein a subsequent read comprises one of a read initiated by a storage region testing module and a read from a read request.

11. The apparatus of claim 5, further comprising an area reconfiguration module that replaces data in the one or more storage regions in the selected memory device with replacement data from one or more extra memory devices for future operations such that data outside the one or more storage regions in the selected memory device is not replaced.

12. The apparatus of claim 11, wherein the area reconfiguration module replaces data from the one or more storage regions on a selected memory device with replacement data from one or more extra memory devices and replaces data from one or more additional storage regions on the same selected memory device or a different selected memory device with replacement data from the same one or more extra memory devices, each of the one or more additional storage regions comprising one or more errors, wherein the one or more storage regions and the one or more additional storage regions do not share a common logical page.

13. The apparatus of claim 11, wherein the area reconfiguration module replaces data from the one or more storage regions with replacement data from one or more extra memory devices and replaces one or more additional storage regions with replacement data from one or more different extra memory devices, each of the one or more additional storage regions comprising one or more errors, wherein the one or more storage regions and the one or more additional storage regions share a common logical page.

14. The apparatus of claim 5, wherein a storage region comprises one or more of one or more ECC chunks, one or more physical pages, one or more logical pages, one or more physical erase blocks, one or more logical erase blocks, a chip, a portion of a chip, a portion of one or more dies, and one or more dies.

15. The apparatus of claim 5, further comprising an analysis module that analyzes the log to determine one or more of an area in the selected memory device with data errors and an error type.

16. The apparatus of claim 1, further comprising an error storage recovery module that erases an erase block with the one or more errors to prepare the erase block for future data storage in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC.

17. The apparatus of claim 16, wherein the retirement module retires the erase block and uses replacement data from the one or more extra memory devices in place of data from the erase block in response to

the storage error recovery module erasing the erase block, subsequently writing additional data to the erase block, a subsequent read of the additional data by the read module, and using the ECC module and the isolation module to determine that the erase block comprises uncorrectable errors that are correctable by combining replacement data with available data.

18. The apparatus of claim 1, wherein the read module reads the data from at least a portion of a logical page, the logical page spanning the array of memory devices, the array of memory devices comprising an array of N+P number of storage elements, the array of storage elements comprising N number of the storage elements each storing a portion of an ECC chunk and P number of the storage elements storing parity data, the ECC chunk comprising stored data and ECC generated from the stored data wherein the ECC spans the stored data, the P number of storage elements storing parity data generated from the ECC chunk stored in the N number of the storage elements.

19. The apparatus of claim 1, further comprising a correct data module that returns corrected data in response to the ECC module determining that the available data combined with the replacement data contains one of no errors and errors that are correctable using the ECC.

20. The apparatus of claim 1, further comprising a reporting module that reports the error in response to the ECC module determining that the available data combined with the replacement data contains errors that not are correctable using the ECC.

21. The apparatus of claim 1, wherein each memory device comprises non-volatile solid state storage.

22. A system to detect and replace failed data storage, the system comprising:

an array of memory devices, the array comprising two or more memory devices and one or more extra memory devices, the extra memory devices storing parity information from the memory devices;

a storage controller controlling the array;

a read module that reads data from the array of memory devices;

an ECC module that determines, using an error correcting code (“

ECC”

), if one or more errors exist in tested data and if the errors are correctable using the ECC, the tested data comprising data read by the read module;

an isolation module that

selects a memory device from the array of memory devices in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC; and

replaces data read from the selected memory device with data comprising data generated from the parity data stored on the one or more extra memory devices (“

replacement data”

) and data read from the memory devices that are not selected (“

available data”

),

wherein the tested data further comprises the available data combined with the replacement data.

23. A computer program product comprising a computer readable medium having computer usable program code executable to perform operations for detecting and replacing failed data storage, the operations of the computer program product comprising:

reading data from an array of memory devices, the array comprising two or more memory devices and one or more extra memory devices, the extra memory devices storing parity information from the memory devices;

determining if one or more errors exist in tested data using an error correcting code (“

ECC”

) and if the errors are correctable using the ECC, the tested data comprising data read from the array of memory devices;

selecting a memory device from the array of memory devices in response to the ECC module determining that errors exists in the data and that the errors are uncorrectable using the ECC;

replacing data read from the selected memory device with data comprising data generated from the parity data stored on the one or more extra memory devices (“

replacement data”

) and data read from the memory devices that are not selected (“

available data”

); and

determining if the tested data contains one of no errors and errors such that the errors are correctable using the ECC, the tested data further comprising the available data combined with the replacement data.