High shrinkage stress silicon nitride (SiN) layer for NFET improvement

• US 20090289284A1
• Filed: 05/23/2008
• Published: 11/26/2009
• Est. Priority Date: 05/23/2008
• Status: Abandoned Application

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Tian, Jingze, Zhou, Mei Sheng, Lu, Wei, Goh, Luona
• Application Number:
  US12/154,605
• Publication Number:
  US 20090289284A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/3125 layers comprising silazane compounds
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region.

Claims

1. A method of forming a semiconductor structure, the method comprising:

providing a substrate;

forming a stressed layer overlying the substrate for applying tensile stress to a channel region of an n-type field effect transistor (FET), wherein forming the stressed layer comprises,

spin-on deposition of a dielectric material on the substrate,

heating the dielectric material to form a dielectric film, and

curing the dielectric film to shrink the dielectric film thereby forming the stressed layer.

2. The method in accordance with claim 1 wherein the stressed layer forms a contact etch stop layer (CESL).

3. The method in accordance with claim 1 wherein the stressed layer forms a capping layer for applying tensile stress to the channel region in accordance with a stress memorization technique.

4. The method in accordance with claim 1 wherein heating the dielectric material includes heating to a temperature between about 100 and 200 degrees Celsius.

5. The method in accordance with claim 1 wherein curing the dielectric film to form the stressed layer further comprises:

removing a substantial portion of an element from the dielectric material to cause shrinkage in the dielectric film.

6. The method in accordance with claim 5 wherein curing the dielectric film to form the stressed layer further comprises a one of:

thermal curing, ultra-violet (UV) curing, electron beam curing and laser curing.

7. The method in accordance with claim 1 wherein the dielectric material has good etch selectivity and high shrinkage characteristics.

8. The method in accordance with claim 7 wherein the dielectric material comprises polysilazane.

9. The method in accordance with claim 7 wherein the dielectric material is perhydro-polysilazane.

10. The method in accordance with claim 1 wherein the stressed layer applies a tensile stress to the channel region of at least about 1.7 Gpa.

11. A semiconductor substrate having one or more field effect transistors (FETs), the substrate comprising:

a first n-type FET having a source region, a drain region and a gate structure; and

a stressed film overlying the source region, the drain region and the gate structure, the stressed film imparting a tensile stress of at least about 1.7 Gpa within a channel region extending between the source region and the drain region.

12. The substrate in accordance with claim 11 wherein the stressed film functions as a contact etch stop layer (CESL) and comprises silicon nitride formed from a dielectric material spun onto the substrate.

13. The substrate in accordance with claim 11 wherein the stressed film functions as a capping layer to impart the tensile stress through a stress memorization technique and comprises silicon nitride formed from a dielectric material spun onto the substrate.

14. The substrate in accordance with claim 11 wherein the stressed film is formed from polysilazane deposited on the substrate.

15. A method of forming a stressed layer for generating tensile stress within a channel region of a field-effect transistor (FET) in a semiconductor structure, the method comprising:

spinning on a dielectric material over a gate structure, a source region and a drain region of a FET;

heating the dielectric material to form a dielectric film, and

curing the dielectric film to shrink the dielectric film thereby forming the stressed layer.

16. The method in accordance with claim 15 wherein the stressed layer forms a contact etch stop layer (CESL), and the CESL imparts tensile stress to a channel region of the FET.

17. The method in accordance with claim 16 wherein the stressed layer has a thickness less than about 750 Angstroms.

18. The method in accordance with claim 15 wherein the stressed layer forms a capping layer for applying tensile stress to a channel region of the FET in accordance with a stress memorization technique.

19. The method in accordance with claim 15 wherein the dielectric material is perhydro-polysilazane, and curing the dielectric film to form the stressed layer further comprises:

removing a substantial portion of hydrogen from the dielectric material to cause shrinkage in the dielectric film.

20. The method in accordance with claim 15 wherein the stressed layer is formed of multiple layers of dielectric material, with each layer formed by:

spinning on the dielectric material over the gate structure, the source region and the drain region of the FET;

heating the dielectric material to form the dielectric film, and

curing the dielectric film to shrink the dielectric film thereby forming one of the multiple layers of the stressed layer.