SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

• US 20090289300A1
• Filed: 07/30/2009
• Published: 11/26/2009
• Est. Priority Date: 07/27/2007
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Okashita, Katsumi, Nakamoto, Keiichi, Kanada, Hisataka, Mizuno, Bunji, SASAKI, Yuichiro
• Granted Patent: US 8,004,045 B2
• Time in Patent Office: Days
• US Class Current: 257/344
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.

Claims

1. A semiconductor device comprising:

a first fin-shaped semiconductor region formed on a substrate, the first fin-shaped semiconductor region having first-conductivity-type impurity region formed therein;

a second fin-shaped semiconductor region formed on the substrate, the second fin-shaped semiconductor region having second-conductivity-type impurity region formed therein;

a first gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first fin-shaped semiconductor region, the upper corner of the first fin-shaped semiconductor region having a radius of curvature of r1 under the first gate insulating film different from a radius of curvature of r1′

outside the first gate insulating film; and

a second gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the second fin-shaped semiconductor region, the upper corner of the second fin-shaped semiconductor region having a radius of curvature of r2 under the second gate insulating film different from a radius of curvature of r2′

outside the second gate insulating film, wherein

r1′

is greater than r1 and less than or equal to 2×

r1, and

r2′

is greater than r2 and less than or equal to 2×

r2.

2. The semiconductor device of claim 1, wherein

the first-conductivity type impurity region includes a first first-conductivity-type impurity region formed in an upper portion of the first fin-shaped semiconductor regions and a second first-conductivity-type impurity region formed in a side portion of the first fin-shaped semiconductor region, and

the second-conductivity-type impurity region includes a first second-conductivity-type impurity region formed in an upper portion of the second fin-shaped semiconductor region and a second second-conductivity-type impurity region formed in a side portion of the second fin-shaped semiconductor region.

3. The semiconductor device of claim 2, wherein

a sheet resistance of the second first-conductivity-type impurity region is less than or equal to 1.25 times that of the first first-conductivity-type impurity region, and

a sheet resistance of the second second-conductivity-type impurity region is less than or equal to 1.25 times that of the first second-conductivity-type impurity region.

4. The semiconductor device of claim 2, wherein

a resistivity of the second first-conductivity-type impurity region is less than or equal to 1.25 times that of the first first-conductivity-type impurity region, and

a resistivity of the second second-conductivity-type impurity region is less than or equal to 1.25 times that of the first second-conductivity-type impurity region.

5. The semiconductor device of claim 2, wherein

a spreading resistance of the second first-conductivity-type impurity region is less than or equal to 1.25 times that of the first first-conductivity-type impurity region, and

a spreading resistance of the second second-conductivity-type impurity region is less than or equal to 1.25 times that of the first second-conductivity-type impurity region.

6. The semiconductor device of claim 2, wherein

a junction depth of the second first-conductivity-type impurity region is substantially equal to or greater than that of the first first-conductivity-type impurity region, and

a junction depth of the second second-conductivity-type impurity region is substantially equal to or greater than that of the first second-conductivity-type impurity region.

7. The semiconductor device of claim 2, further comprising:

a first gate electrode formed on the first gate insulating film; and

a second gate electrode formed on the second gate insulating film, wherein

the first first-conductivity-type impurity region and the second first-conductivity-type impurity region are formed in another portion of the first fin-shaped semiconductor region other than the predetermined portion, and

the first second-conductivity-type impurity region and the second second-conductivity-type impurity region are formed in another portion of the second fin-shaped semiconductor region other than the predetermined portion.

8. The semiconductor device of claim 7, wherein

the first gate insulating film is formed also on an upper surface of the predetermined portion of the first fin-shaped semiconductor region, and

the second gate insulating film is formed also on an upper surface of the predetermined portion of the second fin-shaped semiconductor region.

9. The semiconductor device of claim 7, wherein

the first first-conductivity-type impurity region and the second first-conductivity-type impurity region are p-type extension regions, and

the first second-conductivity-type impurity region and the second second-conductivity-type impurity region are n-type extension regions.

10. The semiconductor device of claim 7, further comprising:

a first insulative sidewall spacer formed on a side surface of the first gate electrode;

a second insulative sidewall spacer formed on a side surface of the second gate electrode;

a third first-conductivity-type impurity region formed in the upper portion of the first fin-shaped semiconductor region;

a fourth first-conductivity-type impurity region formed in the side portion of the first fin-shaped semiconductor region;

a third second-conductivity-type impurity region formed in the upper portion of the second fin-shaped semiconductor region; and

a fourth second-conductivity-type impurity region formed in the side portion of the second fin-shaped semiconductor region, wherein

the third first-conductivity-type impurity region and the fourth first-conductivity-type impurity region are formed in a portion of the other portion of the first fin-shaped semiconductor region that is located outside the first insulative sidewall spacer, and

the third second-conductivity-type impurity region and the fourth second-conductivity-type impurity region are formed in a portion of the other portion of the second fin-shaped semiconductor region that is located outside the second insulative sidewall spacer.

11. The semiconductor device of claim 10, wherein

the third first-conductivity-type impurity region and the fourth first-conductivity-type impurity region are p-type source-drain regions, and

the third second-conductivity-type impurity region and the fourth second-conductivity-type impurity region are n-type source-drain regions.

12. The semiconductor device of claim 1, wherein

an insulating film is formed between the substrate and each of the first fin-shaped semiconductor region and the second fin-shaped semiconductor region.

13. The semiconductor device of claim 1, wherein

a height of a side surface of the first fin-shaped semiconductor region is greater than a width in a gate width direction of an upper surface of the first fin-shaped semiconductor region, and

a height of a side surface of the second fin-shaped semiconductor region is greater than a width in a gate width direction of an upper surface of the second fin-shaped semiconductor region.

14. The semiconductor device of claim 1, wherein

a width in a gate width direction of an upper surface of each of the first fin-shaped semiconductor region and the second fin-shaped semiconductor region is less than or equal to 20 nm.

15. A method for producing a semiconductor device, comprising the steps of:

(a) forming a first fin-shaped semiconductor region on a substrate;

(b) forming a second fin-shaped semiconductor regions on the substrate;

(c) implanting the first fin-shaped semiconductor region with a first-conductivity-type impurity by a plasma doping method; and

(d) implanting the second fin-shaped semiconductor region with a second-conductivity-type impurity by a plasma doping method, wherein

the first-conductivity-type impurity is a p-type impurity or an n-type impurity,

the second-conductivity-type impurity is an impurity of a conductivity type different from that of the first-conductivity-type impurity,

in a case where a mass of the second-conductivity-type impurity is greater than that of the first-conductivity-type impurity, a pressure during plasma doping in the step (d) is set to be less than or equal to that in the step (c), and

in a case where the mass of the first-conductivity-type impurity is greater than that of the second-conductivity-type impurity, the pressure during plasma doping in the step (c) is set to be less than or equal to that in the step (d).

16. The method of claim 15, wherein

the step (c) includes forming a first first-conductivity-type impurity region in an upper portion of the first fin-shaped semiconductor region and forming a second first-conductivity-type impurity region in a side portion of the first fin-shaped semiconductor region, and

the step (d) includes forming a first second-conductivity-type impurity region in an upper portion of the second fin-shaped semiconductor region and forming a second second-conductivity-type impurity region in a side portion of the second fin-shaped semiconductor region.

17. The method for producing a semiconductor device of claim 16, wherein

in the step (c), an implantation dose of the second first-conductivity-type impurity region is 80% or more of that of the first first-conductivity-type impurity region, and

in the step (d), an implantation dose of the second second-conductivity-type impurity region is 80% or more of that of the first second-conductivity-type impurity region.

18. The method for producing a semiconductor device of claim 15, further comprising the step of:

forming, before the step (c), a first gate insulating film so as to cover at least a side surface and an upper corner of a predetermined portion of the first fin-shaped semiconductor region, wherein

after the step (c), a radius of curvature r1′

of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than a radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film.

19. The method for producing a semiconductor device of claim 18, wherein

after the step (c), r1′

is less than or equal to 2×

r1.

20. The method for producing a semiconductor device of claim 15, further comprising forming, before the step (d), a second gate insulating film so as to cover at least a side surface and an upper corner of a predetermined portion of the second fin-shaped semiconductor region, wherein

after the step (d), a radius of curvature r2′

of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than a radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film.

21. The method for producing a semiconductor device of claim 20, wherein

after the step (d), r2′

is less than or equal to 2×

r2.

22. The method for producing a semiconductor device of claim 15, wherein

a mass of the second-conductivity-type impurity is greater than that of the first-conductivity-type impurity,

in the step (c), an ion current density during plasma doping is set to be less than or equal to 0.5 mA/cm², and

in the step (d), the ion current density during plasma doping is set to be less than or equal to 0.1 mA/cm².

23. The method for producing a semiconductor device of claim 15, wherein

a mass of the second-conductivity-type impurity is greater than that of the first-conductivity-type impurity,

the first-conductivity-type impurity is boron,

the second-conductivity-type impurity is arsenic or phosphorus,

the step (c) is performed by using a plasma generated from a gas containing the first-conductivity-type impurity, and

the step (d) is performed by using a plasma generated from a gas containing the second-conductivity-type impurity.

24. The method for producing a semiconductor device of claim 15, wherein

the step (c) is performed by using a plasma generated from a first gas containing the first-conductivity-type impurity,

the step (d) is performed by using a plasma generated from a second gas containing the second-conductivity-type impurity,

the first gas is a gas obtained by diluting molecules containing the first-conductivity-type impurity with helium, and

the second gas is a gas obtained by diluting molecules containing the second-conductivity-type impurity with helium.

25. The method for producing a semiconductor device of claim 15, wherein

the step (c) is performed by using a plasma generated from a first gas containing the first-conductivity-type impurity,

the step (d) is performed by using a plasma generated from a second gas containing the second-conductivity-type impurity, and

one of the first gas and the second gas is a mixed gas of B₂H₆ and He.

26. The method for producing a semiconductor device of claim 15, wherein

the step (c) is performed by using a plasma generated from a first gas containing the first-conductivity-type impurity,

the step (d) is performed by using a plasma generated from a second gas containing the second-conductivity-type impurity, and

one of the first gas and the second gas is a mixed gas of AsH₃ and He.

27. The method for producing a semiconductor device of claim 15, wherein

the step (c) is performed by using a plasma generated from a first gas containing the first-conductivity-type impurity,

the step (d) is performed by using a plasma generated from a second gas containing the second-conductivity-type impurity, and

one of the first gas and the second gas is mixed gas of PH₃ and He.

28. The method for producing a semiconductor device of claim 15, wherein

the first-conductivity-type impurity is a p-type impurity and the second-conductivity-type impurity is an n-type impurity, and

a pressure during the step (c) is set so as to be less than or equal to 0.6 Pa and the pressure during the step (d) is set so as to be less than or equal to 0.4 Pa.