METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

• US 20090289309A1
• Filed: 05/21/2008
• Published: 11/26/2009
• Est. Priority Date: 05/21/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: HSIA, Liang Choo, LU, Wei, LIU, Huang, SEE, Alex KH, CONG, Hai, ZHOU, Mei Sheng, KOH, Hui Peng, YE, Jianhui
• Granted Patent: US 7,745,320 B2
• Time in Patent Office: Days
• US Class Current: 257/384
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Claims

1. An integrated circuit (IC) having a transistor comprising:

a gate on a substrate, the gate having gate sidewalls;

diffusion regions in the substrate adjacent to the gate;

reduced dielectric spacers disposed on the gate sidewalls; and

metal silicide contacts over the diffusion regions, wherein outer walls of the reduced dielectric spacers have been pulled back to be in alignment with the metal silicide contacts to reduce stress on the metal silicide contacts.

2. A method for forming a transistor in an integrated circuit (IC) comprising:

providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate;

forming dielectric spacers on the gate sidewalls;

forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and

pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts to reduce stress on the metal silicide contacts.

3. The method of claim 2 wherein forming the metal silicide contacts comprises performing first and second annealing processes.

5. The method of claim 2 wherein pulling back the dielectric spacers comprises an anisotropic etch.

6. The method of claim 2 wherein forming the metal silicide contacts comprises performing first and second annealing processes.

7. The method of claim 6 wherein pulling back the dielectric spacers is performed between the first and second annealing processes.

8. The method of claim 7 wherein pulling back the dielectric spacers comprises an anisotropic etch.

9. The method of claim 2 comprises:

cleaning the substrate surface after forming the dielectric spacers, the cleaning forms undercut regions in a lower portion of the dielectric spacers such that edge portions of the metal silicide contacts are disposed in the undercut regions; and

pulling back the dielectric spacers after metal silicide contacts are formed to align the outer walls of the dielectric spacers with edges of the metal silicide contacts.

10. The method of claim 9 wherein pulling back the dielectric spacers comprises an anisotropic etch.

11. The method of claim 10 wherein forming the metal silicide contacts comprises performing first and second annealing processes.

12. The method of claim 11 wherein pulling back the dielectric spacers is performed between the first and second annealing processes.

13. The method of claim 2 wherein the metal silicide contacts comprises nickel or nickel alloy.

4. (canceled)

14. A method for reducing metal pipes comprising:

providing a feature on a substrate;

forming dielectric spacers on sidewalls of the feature; and

forming metal silicide contacts on the substrate adjacent to the dielectric spacers, wherein portions of the metal silicide contacts are covered by the spacers; and

pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts, wherein aligning the edges of the dielectric spacers and metal silicide contacts reduces formation of metal pipes.

15. The method of claim 14 comprises pulling back the dielectric spacers to align the outer walls of the dielectric spacers with the edges of the metal silicide contacts.

16. The method of claim 15 wherein pulling back the dielectric spacers comprises an anisotropic etch.

17. The method of claim 15 wherein forming the metal silicide contacts comprises performing first and second annealing processes and pulling back the dielectric spacers is performed between the first and second annealing processes.

18. The method of claim 17 wherein pulling back the dielectric spacers comprises an anisotropic etch.

19. The method of claim 14 wherein the feature comprises a gate of a transistor.

20. The method of claim 19 comprises pulling back the dielectric spacers to align the outer walls of the dielectric spacers with the edges of the metal silicide contacts.

21. A method of fabricating an integrated circuit comprising:

providing a semiconductor body having STI, gate and spacer structures;

forming a Ni or NiPt layer over the structures;

forming TiN cap layer over the structures;

forming first phase Ni silicide layer via RTA1 at 300-400°

C., wherein portions of the Ni silicide layer are covered by the spacers;

performing wet clean to remove the TiN cap and unreacted Ni;

dry (plasma) etching of the spacer to have spacer pull-back, wherein outer walls of the spacers are aligned with edges of the Ni silicide contacts;

forming second phase Ni silicide layer via RTA2 at 400-600°

C.

22. The method of claim 21 wherein the Ni or NiPt is deposited using physical vapor deposition.

23. The method of claim 21 wherein the dry etching of the spacer to have spacer pull-back reduces stress of SiN on active and STI divot areas.