Annealing a Buffer Layer for Fabricating Electronic Devices on Compliant Substrates

• US 20090289333A1
• Filed: 05/20/2008
• Published: 11/26/2009
• Est. Priority Date: 05/20/2008
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Greer, Julia R., Wong, William S., Lujan, Rene
• Granted Patent: US 8,465,795 B2
• Time in Patent Office: Days
• US Class Current: 257/640
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate

Abstract

A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

Claims

1. A method of manufacturing a layered electronic device over a flexible substrate, comprising:

forming a buffer layer over said flexible substrate;

heating said buffer layer and flexible substrate to an anneal temperature which is greater than the temperature at which the buffer layer plastically deforms;

cooling the buffer layer and flexible substrate; and

forming over said buffer layer and flexible substrate a thin-film layered electronic device at a temperature that does not exceed said anneal temperature.

2. The method of claim 1, wherein said buffer layer comprises:

a stacked structure of silicon dioxide and silicon nitride.

3. The method of claim 2, wherein said buffer layer is formed to be silicon dioxide layer in the range of 200-400 nanometers thick formed over a silicon nitride layer in the range of 200-400 nanometers thick.

4. The method of claim 3, wherein each of said silicon dioxide and said silicon nitride layers are approximately of the same thickness.

5. The method of claim 4, wherein each of said silicon dioxide and said silicon nitride layers are each approximately 300 nanometers thick.

6. The method of claim 1, wherein said substrate is polyethylene naphthalate.

7. The method of claim 1, further comprising:

forming said buffer layer over said flexible substrate under vacuum pressure within a vacuum chamber; and

wherein said step of heating is performed for approximately 30 minutes while maintaining the substrate and buffer layer under said vacuum pressure within said vacuum chamber, and further wherein the temperature within said vacuum chamber during said step of heating is approximately 180°

C.

8. The method of claim 1, further comprising:

depositing a base metal layer over said buffer layer, before said heating and cooling, said base metal layer forming the base for subsequent thin-film deposition and processing, and thereafter performing said heating and cooling steps.

9. The method of claim 8, wherein said base metal layer is formed of tantalum, and is formed to be in the range of approximately 100-150 nanometers thick.

10. The method of claim 9, wherein said base metal layer is formed to be approximately 120 nanometers thick.

11. The method of claim 8, further comprising:

forming said buffer layer over said flexible substrate and said base metal layer over said buffer layer under vacuum pressure within a vacuum chamber; and

wherein said step of heating is performed for approximately 30 minutes while maintaining the substrate and buffer layer under said vacuum pressure within said vacuum chamber, and further wherein the temperature within said vacuum chamber during said step of heating is approximately 180°

C.

12. A thin-film electronic structure comprising:

a flexible substrate and buffer layer formed thereover in which, following formation of said buffer layer over said flexible substrate said buffer layer has been plastically deformed by an annealing during which said substrate and said buffer layer are heated to an anneal temperature then cooled; and

a thin-film layered device, formed over said plastically deformed buffer layer and flexible substrate such that the buffer layer is not plastically deformed beyond that deformation caused by said annealing by the formation of said thin-film layered device.

13. The thin-film electronic structure of claim 12, wherein said buffer layer comprises a stacked structure of silicon dioxide and silicon nitride.

14. The thin-film electronic structure of claim 13, wherein said buffer layer comprises:

a silicon nitride layer in the range of 200-400 nanometers thick formed over said substrate; and

a silicon dioxide layer in the range of 200-400 nanometers thick formed over said silicon nitride layer.

15. The thin-film electronic structure of claim 14, wherein said silicon dioxide and said silicon nitride layers are approximately the same thickness.

16. The thin-film electronic structure of claim 15, wherein said silicon dioxide and said silicon nitride layers are each approximately 300 nanometers thick.

17. The thin-film electronic structure of claim 12, wherein said flexible substrate is polyethylene naphthalate.

18. The thin-film electronic structure of claim 12, further comprising:

a base metal layer, formed over said buffer layer before said annealing and before formation of said thin-film layered device.

19. The thin-film electronic structure of claim 18, wherein said base metal layer is formed of tantalum, and is in the range of approximately 100-150 nanometers thick.

20. The thin-film electronic structure of claim 19, wherein said base metal layer is approximately 120 nanometers thick.