SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION

• US 20090289348A1
• Filed: 05/21/2009
• Published: 11/26/2009
• Est. Priority Date: 05/23/2008
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Hall, Jeffrey A., Jin, Wenyi, Zhong, Freeman Y., Zhong, Lizhi, Tang, George C.
• Granted Patent: US 8,324,019 B2
• Time in Patent Office: Days
• US Class Current: 257/697
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0219 Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 1/112 directly combined with via connections

Abstract

A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Claims

1. A method of minimizing crosstalk in a package of an integrated circuit, comprising the steps of:

(A) routing a first signal of a first full-duplex channel between two or more first pads of a plurality of external pads and a first trace layer within said package in an congested area of said package, wherein (i) said external pads are disposed on an integrated circuit side of said package and (ii) said first trace layer is proximate said integrated circuit side;

(B) routing said first signal between said first trace layer and a second trace layer within said package in an non-congested area of said package, wherein (i) said second trace layer is proximate a pin side of said package and (ii) said pin side is opposite said integrated circuit side;

(C) routing said first signal between said second trace layer and two or more first pins of a plurality of external pins in said non-congested area, wherein said external pins are disposed on said pin side of said package;

(D) routing a second signal of said first full-duplex channel between two or more second pads of said external pads and said first trace layer in said congested area of said package;

(E) routing said second signal between said first trace layer and said second trace layer in said congested area of said package; and

(F) routing said second signal between said second trace layer and two or more second pins of said external pins in said non-congested area, wherein (i) all of said first pins and said second pins are arranged along a first line in a first direction and (ii) said first pins are offset from said second pins by a gap in said first direction of at least two inter-pin spaces.

2. The method according to claim 1, further comprising the step of:

routing at least one power voltage through at least one power pin of said external pins, wherein said at least one power pin (i) is disposed on said first line in said gap and (ii) shields first signal from said second signal.

3. The method according to claim 1, further comprising the step of:

routing at least one power voltage through a third trace layer within said package, wherein said third trace layer (i) is disposed between said first trace layer and said second trace layer and (ii) shields said first signal from said second signal.

4. The method according to claim 1, further comprising the step of:

routing a third signal of a second full-duplex channel between two or more third pins of said external pins and two or more third pads of said external pads, wherein (i) said third pins are (a) directly adjacent to said first pins in a second direction and (b) staggered by at least one of said inter-pin spaces in said first direction from said first pins and (ii) said second direction is perpendicular to said first direction.

5. The method according to claim 4, further comprising the step of:

routing a fourth signal of said second full-duplex channel between two or more fourth pins of said external pins and two or more fourth pads of said external pads, wherein (i) all of said third pins and said fourth pins are arranged along a second line in said first direction and (ii) said third pins are offset from said fourth pins by said gap in said first direction.

6. The method according to claim 1, further comprising the steps of:

routing said first signal through a plurality of first vias between said first pads and said first trace layer in said congested area, wherein each of said first vias has a first diameter; and

routing said first signal through a plurality of second vias between said first trace layer and said second trace layer in said non-congested area, wherein each of said second vias has a second diameter larger than said first diameter.

7. The method according to claim 6, further comprising the step of:

routing said first signal through a plurality of third vias between said second trace layer and said first pins in said non-congested area, wherein each of said third vias has said first diameter.

8. The method according to claim 6, further comprising the steps of:

routing said second signal between said second pads and said first trace layer through said first vias in said congested area; and

routing said second signal through said second vias between said first trace layer and said second trace layer in said congested area.

9. The method according to claim 8, further comprising the steps of:

routing said second signal through a plurality of third vias between said second trace layer and said second pins in said non-congested area, wherein each of said third vias has said first diameter.

10. The method according to claim 1, wherein (i) said first signal comprises a differential receive signal and (ii) said second signal comprises a differential transmit signal.

11. An apparatus comprising:

a package having (i) a integrated circuit side, (ii) a pin side opposite said integrated circuit side a (iii) a first trace layer proximate said integrated circuit side and (iv) a second trace layer proximate said pin side;

a plurality of external pins disposed on said pin side of said package; and

a plurality of external pads disposed on said integrated circuit side of said package, wherein

(i) a first signal of a first full-duplex channel is routed between (a) two or more first pads of said external pads and said first trace layer in a congested area of said package, (b) said first trace layer and said second trace layer in an non-congested area of said package and (c) said second trace layer and two or more first pins of said external pins in said non-congested area,

(ii) a second signal of said first full-duplex channel is routed between (a) two or more second pads of the external pads and said first trace layer in said congested area, (b) said first trace layer and said second trace layer in said congested area and (c) said second trace layer and two or more second pins of said external pins in said non-congested area,

(iii) all of said first pins and said second pins are arranged along a first line in a first direction, and

(iv) said first pins are offset from said second pins by a gap in said first direction of at least two inter-pin spaces.

12. The apparatus according to claim 11, further comprising at least one power pin of said external pins (i) disposed on said first line in said gap and (ii) shielding said first signal from said second signal.

13. The apparatus according to claim 11, further comprises a third trace layer (i) disposed between said first trace layer and said second trace layer and (ii) shielding said first signal from said second signal.

14. The apparatus according to claim 11, further comprising two or more third pins of said external pins and two or more third pads of said external pads routing a third signal of a second full-duplex channel, wherein (i) said third pins are (a) directly adjacent to said first pins in a second direction and (b) staggered by at least one of said inter-pin spaces in said first direction from said first pins and (ii) said second direction is perpendicular to said first direction.

15. The apparatus according to claim 14, further comprising two or more fourth pins of said external pins and two or more fourth pads of said external pads routing a fourth signal of said second full-duplex channel, wherein (i) all of said third pins and said fourth pins are arranged along a second line in said first direction and (ii) said third pins are offset from said fourth pins by said gap in said first direction.

16. The apparatus according to claim 11, further comprising:

a plurality of first vias routing said first signal between said first pads and said first trace layer in said congested area, wherein each of said first vias has a first diameter; and

a plurality of second vias routing said first signal between said first trace layer and said second trace layer in said non-congested area, wherein each of said second vias has a second diameter larger than said first diameter.

17. The apparatus according to claim 16, further comprising a plurality of third vias routing said first signal between said second trace layer and said first pins in said non-congested area, wherein each of said third via has said first diameter.

18. The apparatus according to claim 16, wherein (i) said first vias route said second signal between said second pads and said first trace layer in said congested area and (ii) said second vias route said second signal between said first trace layer and said second trace layer in said congested area.

19. The apparatus according to claim 18, further comprising a plurality of third vias routing said second signal between said second trace layer and said second pins in said non-congested area, wherein each of said third vias has said first diameter.

20. The apparatus according to claim 11, wherein (i) said first pads are proximate an outer edge of said integrated circuit and (ii) said second pads are proximate a center of said integrated circuit.