Opto-Isolator Multi-Voltage Detection Circuit

• US 20090289575A1
• Filed: 05/21/2009
• Published: 11/26/2009
• Est. Priority Date: 05/23/2008
• Status: Active Grant

• Current Assignee: Fisher Controls International LLC (Emerson Electric Company)
• Original Assignee: Fisher Controls International LLC (Emerson Electric Company)
• Inventors: Seberger, Stephen G., Eisenbeis, Clyde T.
• Granted Patent: US 8,570,770 B2
• Time in Patent Office: Days
• US Class Current: 315/291
• CPC Class Codes: G01R 15/22 using light-emitting devices, e.g. LED, optocouplers G01R31/31901 takes precedence
• CPC Class Codes: G01R 19/155 Indicating the presence of voltage
• CPC Class Codes: G01R 19/16519 using FET's

Abstract

An opto-isolator multi-voltage detection circuit is capable to handle a wide range of input voltages ranging from about 9 volts DC to about 240 volts AC includes an input voltage, an opto-isolator, a rectifier, a voltage divider, first and second transistors, and a DC to DC converter. The voltage divider operatively coupled to the first and second transistors is capable of evenly dividing the input voltage across the first and second transistors. The DC to DC converter operatively coupled to the transistors, the voltage divider, and the opto-isolator is capable of maintaining an output current from the rectifier. The use of the DC to DC converter, the voltage divider, and the transistors provide benefit of reducing a power dissipated throughout the entire circuit.

Claims

1. An opto-isolator multi-voltage detection circuit comprising:

a voltage input, the voltage input arranged for connection to the voltage source;

an opto-isolator having a light-emitting diode (LED), the opto-isolator configured to detect the presence of an input voltage applied to the voltage input from the voltage source;

a diode, the diode arranged for connection to the voltage input; and

a first transistor having a gate, a source, and a drain, the drain of the first transistor operatively coupled to the diode, and the source of the first transistor operatively coupled to the opto-isolator;

the opto-isolator, the diode, and the first transistor arranged such that a current flowing forward from the diode biases the LED, and further such that any power dissipated through the first transistor in response to the input voltage and to the current is maintained at or below an acceptable level.

2. The circuit of claim 1, further comprising a DC to DC converter operatively coupled to the source of the first transistor and the opto-isolator, the DC to DC converter configured to maintain the current from the diode.

3. The circuit of claim 2, further comprising:

a second transistor having a gate, a source, and a drain, the source of the second transistor serially coupled to the drain of the first transistor, the drain of the second transistor operatively coupled to the diode; and

a voltage divider operatively coupled to the gates of the first and second transistors, the voltage divider configured to evenly divide the input voltage across the first and second transistors;

wherein the power dissipated through the first transducer and further through the second transistor is maintained at or below an acceptable level, and wherein the circuit is capable to handle the input voltage ranging from about 9 volt DC through 240 volt AC.

4. The circuit of claim 3, further comprising a rectifier, the rectifier operatively coupled to the diode, the voltage divider, and the drain of the second transistor.

5. The circuit of claim 4, wherein the rectifier comprises a resistor, or a capacitor, or a combination thereof.

6. The circuit of claim 4, wherein the first and second transistors are N channel depletion mode field-effect transistor (FET).

7. The circuit of claim 1 further comprising:

a second transistor having a gate, a source, and a drain, the source of the second transistor operatively coupled to the drain of the first transistor;

a first zener diode, the first zener diode arranged for connection to the source and the drain of the first transistor; and

a second zener diode, the second zener diode arrange for connection to the source and the drain of the second transistor;

wherein the first and second zener diodes are configured to limit the input voltage to the first and second transistors, and wherein the power dissipated through the first transducer and further through the second transistor is maintained at or below an acceptable level, and wherein the circuit is capable to handle the input voltage ranging from about 9 volt DC through 240 volt AC.

8. The circuit of claim 7, wherein the first and second transistors are N channel depletion mode field-effect transistor (FET).

9. The circuit of claim 1 further comprising:

a second transistor having a gate, a source, and a drain, the source of the second transistor operatively coupled to the drain of the first transistor; and

a voltage divider operatively coupled to the gates of the first and second transistors;

wherein the power dissipated through the first transducer and further through the second transistor is maintained at or below an acceptable level, and wherein the circuit is capable to handle the input voltage ranging from about 9 volt DC through 240 volt AC.

10. The circuit of claim 9, further comprising a rectifier, the rectifier operatively coupled to the diode, the voltage divider, and the drain of the second transistor.

11. The circuit of claim 10, wherein the rectifier comprises a resistor, or a capacitor, or a combination thereof.

12. The circuit of claim 10, wherein the first and second transistors are N channel depletion mode field-effect transistor (FET).

13. An opto-isolator multi-voltage detection circuit comprising:

a voltage input, the voltage input arranged for connection to the voltage source;

an opto-isolator having a light-emitting diode (LED), the opto-isolator configured to detect the presence of an input voltage applied to the voltage input from the voltage source;

a rectifier, the rectifier arranged for connection to the voltage input; and

a first transistor and a second transistor operatively coupled in series, each transistor having a gate, a source, and a drain, the source of the first transistor operatively coupled to the drain of the second transistor, and the drain of the first transistor operatively coupled to the rectifier;

wherein a current output from the rectifier biases the LED, and wherein the first and second transistors are configured to dissipate a first power level across the first and second transistors, the first power level different than a second power level dissipated across the circuit.

14. The circuit of claim 13, further comprising a voltage divider operatively coupled to the gates of the first and second transistors and the rectifier, and wherein the first power level dissipated across the first and second transistors in response to the input voltage divided across the first and second transistors by the voltage divider is different than the second power level dissipated across the circuit.

15. The circuit of claim 14, wherein the rectifier comprises a capacitor, a resistor, and a diode operatively coupled in series, wherein the diode is connected to the voltage input, and wherein the capacitor is operatively coupled to the voltage divider and to at least one of the gates of the first and second transistors.

16. The circuit of claim 15, further comprising a DC to DC converter operatively coupled to the opto-isolator and at least one of the sources of the first and second transducers, and wherein the DC to DC converter is configured to maintain the current from the first and second transistors.

17. The circuit of claim 13, further comprising:

first and second zener diodes operatively coupled to the first and second transistors, the first and second zener diodes configured to limit the input voltage to the first and second transistors.

18. The circuit of claim 17, wherein either the first zener diode or the second zener diode is operatively coupled to the rectifier, and wherein the rectifier comprises a diode.

19. An opto-isolator multi-voltage detection circuit comprising:

a voltage input, the voltage input arranged for connection to the voltage source;

an opto-isolator having a light-emitting diode (LED), the opto-isolator configured to detect the presence of an input voltage applied to the voltage input from the voltage source;

a diode, a resistor, and a capacitor connected in series and cooperating to define a rectifier, the rectifier connected to the voltage input;

a first transistor and a second transistor operatively coupled in series, each transistor having a gate, a source, and a drain, the source of the first transistor connected to the drain of the second transistor, and the drain of the first transistor connected to the rectifier;

a voltage divider connected to the gates of the first and second transistors, the voltage divider configured to divide the input voltage across the first and second transistors; and

a DC to DC converter connected to the source of the second transistor and the opto-isolator;

wherein a current output from the DC to DC converter biases the LED, and wherein the first and second transistors are configured to dissipate a first power level across the first and second transistors, the first power level different than a second power level dissipated across the circuit.

20. A method for handling a variety of input voltages from a voltage source comprising:

operatively coupling an opto-isolator to a voltage input to detect the presence of the input voltage applied to the voltage input from the voltage source;

forward biasing a light-emitting diode (LED) of the opto-isolator when a current from a diode operatively to the voltage input is detected; and

operatively coupling a first transistor to the diode and the opto-isolator;

wherein maintaining any power dissipated through the first transistor at or below an acceptable level.

21. The method of claim 20, further comprising:

operatively coupling a second transistor to the first transistor to maintain the power dissipation through the first transistor and further through the second transistor at or below the acceptable level.

22. The method of claim 21 further comprising:

operatively coupling a first zener diode to the first transistor; and

operatively coupling a second zener diode to the second transistor;

wherein the first and second zener diodes limit the input voltage across the first and second transistors, and wherein maintaining the power dissipation through the first and second transistors at or below the acceptable level.

23. The method of claim 21 further comprising:

operatively coupling a voltage divider to the first and second transistors;

using a voltage divider to divide the input voltage across the first and second transistors, and wherein maintaining the power dissipation through the first and second transistors at or below the acceptable level.

24. The method of claim 23 further comprising:

operatively coupling a DC to DC converter to the first transistor and the opto-isolator for maintaining the current from the diode.