ELECTRICAL OVERSTRESS AND TRANSIENT LATCH-UP PULSE GENERATION SYSTEM, CIRCUIT, AND METHOD
First Claim
1. In a system to test a device, a pulse generation circuit operable to selectively apply a first test signal to test an electrical overstress characteristic of the device and a second test signal to test a transient induced latch-up characteristic of the device.
2 Assignments
0 Petitions
Accused Products
Abstract
A circuit arrangement, system, and method to test a device with a plurality of pins for electric overstress and transient induced latch-up characteristics. The circuit arrangement includes an inverting operational amplifier with a unity gain to receive a triggering signal and supply an inverted signal to a power amplifier. The power amplifier transforms the inverted signal into a test signal, which is received by a ratio circuit. The test signal is further operable to test the electric overstress and transient induced latch-up characteristics of the device. The ratio circuit transforms the test signal into a ratio signal. The ratio signal has a voltage magnitude that corresponds to the current magnitude of the test signal. The test signal and ratio signal are measured to determine if, during testing, the device or a component of the device has failed.
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Citations
35 Claims
- 1. In a system to test a device, a pulse generation circuit operable to selectively apply a first test signal to test an electrical overstress characteristic of the device and a second test signal to test a transient induced latch-up characteristic of the device.
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6. A circuit arrangement to produce a test signal and a ratio signal, the test signal used to test a device, the circuit comprising:
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a trigger signal generation circuit operable to generate a triggering signal; and a pulse generation circuit responsive to the triggering signal and operable to generate a test signal to be applied to the device and a ratio signal indicative of a current applied to the device by the test signal. - View Dependent Claims (7, 8, 9, 10)
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11. A circuit arrangement to produce a test signal and a ratio signal, the test signal used to test a device, the circuit comprising:
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an inverting operational amplifier with a unity gain, the inverting operational amplifier operable to receive a triggering signal and transform the triggering signal into an inverted signal; a power amplifier electrically coupled with the inverting operational amplifier, the power amplifier operable to receive the inverted signal and transform the inverted signal into the test signal, the test signal used to test at least one of a transient induced latch-up or an electrical overstress characteristic of the device; and a ratio circuit electrically coupled with the power amplifier, the ratio circuit operable to receive the test signal and transform the test signal into the ratio signal, the ratio signal such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A system to test a transient induced latch-up or an electrical overstress characteristic of a device of the type that includes a plurality of pins, the system comprising:
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a pulse generation circuit operable to produce a test signal and a ratio signal, the pulse generation circuit including an inverting operational amplifier having a unity gain and electrically coupled with a digital-to-analog converter, the inverting operational amplifier operable to receive a triggering signal from the digital-to-analog converter and transform the triggering signal into an inverted signal, a power amplifier electrically coupled to the inverting operational amplifier, the power amplifier operable to receive the inverted signal and transform the inverted signal into the test signal, and a ratio circuit electrically coupled to the power amplifier, the ratio circuit operable to receive the test signal and transform the test signal into the ratio signal, the ratio signal such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal; a relay pin matrix electrically coupled to the pulse generation circuit, the relay pin matrix operable to receive the test signal and the device, the relay pin matrix programmatically controlled to relay the test signal to at least one pin from among the plurality of pins of the device to test the transient induced latch-up or electrical overstress characteristic of the device; an oscilloscope electrically coupled with the pulse generation circuit, the oscilloscope operable to measure the test signal and the ratio signal; and a controller electrically coupled to the analog-to-digital converter, oscilloscope, and relay pin matrix, the controller operable to interface with the oscilloscope and store the measured test signal and ratio signal, the controller operable to programmatically control the relay pin matrix to relay the test signal to the at least one pin from among the plurality of pins of the device, the controller operable to provide an analog triggering signal to be converted into the triggering signal by the analog-to-digital converter. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of testing a device of the type that includes a plurality of pins with a system comprising a pulse generation circuit, a relay pin matrix, an oscilloscope, and a controller, wherein the pulse generation circuit is electrically coupled with the relay pin matrix, oscilloscope, and controller, and wherein the controller is electrically coupled with the relay pin matrix and oscilloscope, the method comprising:
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programmatically controlling the relay pin matrix with the controller to relay a signal from the pulse generation circuit to at least one pin from among the plurality of pins of the device; producing a triggering signal with the controller; transforming the triggering signal into a test signal and a ratio signal with the pulse generation circuit, wherein the test signal is operable to test at least one of a transient induced latch-up or an electrical overstress characteristic of the device, transforming the triggering signal into the test signal and the ratio signal further comprising; converting the triggering signal with an analog-to-digital converter, receiving the converted triggering signal at the pulse generation circuit, transforming the triggering signal into an inverted signal with an inverting operational amplifier having a unity gain in the pulse generation circuit, transforming the inverted signal into the test signal with the power amplifier electrically coupled with the inverting operational amplifier, wherein the test signal is the signal relayed to the at least one pin of the device, and transforming the test signal into the ratio signal with a ratio circuit electrically coupled with the power amplifier in the pulse generation circuit, wherein the ratio signal is such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal; measuring the test signal and the ratio signal with the oscilloscope during the testing; in response to relaying the test signal to at least one pin of the device and measuring the ratio signal, determining at least one of the transient induced latch-up or electrical overstress characteristic of the device. - View Dependent Claims (28, 29)
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30. A method of selectively configuring a pulse generation circuit to output a test signal to test a transient induced latch-up or electrical overstress characteristic of a device of the type that includes a plurality of pins, the method comprising:
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producing a triggering pulse with a controller; transforming the triggering pulse into the test signal and a ratio signal with the pulse generation circuit, the pulse generation circuit electrically coupled with the controller and the device; and testing the device with the test signal. - View Dependent Claims (31, 32, 33, 34, 35)
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Specification