BRIDGE DESIGN FOR SD AND MMC DATA BUSES

• US 20090289662A1
• Filed: 08/03/2009
• Published: 11/26/2009
• Est. Priority Date: 01/11/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Modu Limited (Alphabet Inc.)
• Inventors: Sherman, Itay
• Granted Patent: US 7,812,640 B2
• Time in Patent Office: Days
• US Class Current: 326/86
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively.

Claims

1. A circuit with bi-directional signal transmission, comprising:

a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles;

a second signal source, for generating a second signal comprising one bit per clock cycle during a second plurality of clock cycles;

a first buffer, coupled with said first signal source, that outputs the first signal when the first buffer is enabled;

a second buffer, coupled with said second signal source, that outputs the second signal when the second buffer is enabled;

a plurality of logical gates, coupled with said first signal source, said second signal source, said first buffer and said second buffer, that control enablement of said first buffer and said second buffer, such that (i) at any given clock cycle at least one of said first buffer and said second buffer is disabled, and (ii) when said first buffer and said second buffer are both disabled, subsequent generation of a ‘

0’

bit in the first signal or the second signal causes enablement of said first buffer or said second buffer, respectively.

2. The circuit of claim 1 wherein said plurality of logical gates comprises NAND gates and AND gates.

3. The circuit of claim 1 wherein said first buffer and said second buffer are tri-state buffers.

4. The circuit of claim 1 wherein said plurality of gates further control enablement of said first buffer and said second buffer such that (iii) generation of two consecutive “

1”

bits in the first or second signal causes disablement of said first buffer or said second buffer, respectively, when said first buffer or said second buffer respectively were enabled.

5. The circuit of claim 1 wherein said first signal source is coupled with a host device, and said second signal source is coupled with a slave device.

6. The circuit of claim 5 wherein said host device and said slave devices are SD devices.

7. The circuit of claim 5 wherein said host device and said slave devices are MMC devices.

8. The circuit of claim 1 further comprising first and second pull-up resistors, that are operative to generate logical ‘

1’

bits during clock cycles when neither said first signal source nor said second signal source are generating said first and second signals, respectively.

9. A circuit with bi-directional signal transmission, comprising:

a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles;

a second signal source, for generating a second signal comprising one bit per clock cycle during a second plurality of clock cycles;

a first buffer, coupled with said first signal source, that outputs the first signal when the first buffer is enabled;

a second buffer, coupled with said second signal source, that outputs the second signal when the second buffer is enabled;

a plurality of logical gates, coupled with said first signal source, said second signal source, said first buffer and said second buffer, that control enablement of said first buffer and said second buffer, such that there is less than a one clock cycle delay in transmitting the first signal via said first buffer during the first plurality of clock cycles, and in transmitting the second signal via said second buffer during the second plurality of clock cycles.

10. The circuit of claim 9 wherein said first signal source is coupled with a host device, and said second signal source is coupled with a slave device.

11. The circuit of claim 10 wherein said host device and said slave devices are SD devices.

12. The circuit of claim 10 wherein said host device and said slave devices are MMC devices.