DUAL FUNCTION DATA REGISTER
First Claim
1. A data register stage, comprising:
- a data storage circuit having a first latch and a second latch arranged in a master-slave flip-flop configuration for shifting in data serially from a serial input terminal and for shifting out data from a serial output terminal, the shifting operations being controlled by phase adjustable clock signals; and
a status circuit for detecting opposite logic states stored in the first latch and the second latch, and for combining an output corresponding to the detected opposite logic states with a previous local status signal to provide a local status signal, the previous local status signal corresponding to detected opposite logic states stored in a previous data register stage.
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Accused Products
Abstract
A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.
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Citations
23 Claims
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1. A data register stage, comprising:
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a data storage circuit having a first latch and a second latch arranged in a master-slave flip-flop configuration for shifting in data serially from a serial input terminal and for shifting out data from a serial output terminal, the shifting operations being controlled by phase adjustable clock signals; and a status circuit for detecting opposite logic states stored in the first latch and the second latch, and for combining an output corresponding to the detected opposite logic states with a previous local status signal to provide a local status signal, the previous local status signal corresponding to detected opposite logic states stored in a previous data register stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A non-volatile memory device, comprising:
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a memory array having non-volatile memory cells connected to wordlines and bitlines; bitline sense amplifiers coupled to the columns for biasing the bitlines in response to program data in a program operation and for sensing a read voltage of the bitlines in a read operation to provide read data; and a data register for concurrently storing the program data and the read data, the data register comparing the stored program data to the stored read data and providing a status signal corresponding to a successful program operation when the stored program data and the stored read data are opposite logic levels. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification