METHOD AND SYSTEM FOR CONFIGURING FIBRE CHANNEL PORTS

• US 20090290584A1
• Filed: 05/27/2009
• Published: 11/26/2009
• Est. Priority Date: 07/21/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Dropps, Frank R., Papenfuss, Gary M., Kohlwey, Ernest G.
• Granted Patent: US 8,005,105 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/65 Re-configuration of fast packet switches

Abstract

A fibre channel switch element for routing fibre channel frame is provided. The switch element includes a fibre channel port that can be configured to support plural data transfer rates. The data transfer rate may be 1 G, 2 G, 4 G, 8 G or 10 G. The switch element includes a clock configuration module for providing a clock signal that is based on the data transfer rate. A receive segment of the fibre channel port sends a signal to a transmit segment to avoid an under flow condition. The receive segment also waits for a certain frame length after a fibre channel frame is written and before the fibre channel frame is read, depending upon a data transfer rate of a source port. Multiple lanes may be configured as a single 10G multi lane port or as multiple individual ports.

Claims

1-18. -18. (canceled)

19. A switch element for routing information, comprising:

a port that is configured to operate at one or more of a plurality of data transfer rates;

wherein a clock rate for one data transfer rate is not an integer multiple of a clock rate for another data transfer rate at which the same port is configured to operate;

wherein the same port uses one interface to support one or more lanes for receiving and transferring information at the plurality of data transfer rates; and

the one interface includes a plurality of selectable serial/de-serializer (SERDES), where a higher number of SERDES and a higher number of lanes are selected for a first data transfer rate, and a lower number of SERDES and a lower number of lanes are selected for supporting a second data transfer rate, where the first data transfer rate is higher than the second data transfer rate.

20. The element of claim 19, wherein the one data transfer rate is 1 G (gigabit per second).

21. The switch element of claim 19, wherein the one data transfer rate is 2 G (gigabit per second).

22. The switch element of claim 19, wherein the one data transfer rate is 4 G (gigabit per second).

23. The switch element of claim 19, wherein the one data transfer rate is 8 G (gigabit per second).

24. The switch element of claim 19, wherein the one data transfer rate is equal to or greater 10 G (gigabit per second).

25. The switch element of claim 19, wherein the switch element includes a clock configuration module for providing a clock signal that is based on a configured data transfer rate for the same port.

26. The switch element of claim 19, wherein when a source port is operating at a lower data transfer rate than a destination port, a receive segment of the port sends a signal to a transmit segment to avoid an under flow condition.

27. The switch element of claim 26, wherein the receive segment waits for a certain frame length after a frame is written and before the frame is read for transmission, where the certain frame length depends upon a data transfer rate of the source port and the destination port.

28. The switch element of claim 19, wherein multiple lanes are configured for the port to operate as a single 10 G multi lane port and the same port uses the multiple lanes for the same port to operate as a different port at a rate lower than 10 G.

29. The switch element of claim 19, wherein same transmit and receive pipelines are used by the same port configured to operate at different speeds.

30. The switch element of claim 19, wherein transmit and receive pipelines are selected from a plurality of receive pipelines and transmit pipelines, depending upon a data transfer rate at which the port is configured to operate.

31. The switch element of claim 19, wherein a receive buffer for the port is shared by multiple lanes, when the port is configured to operate at different rates.

32. The switch element of claim 19, wherein a separate receive buffer is used for each of the plurality of lanes when the same port is configured to operate at different rates.

33. The switch element of claim 19, wherein each of the plurality of lanes is configured to operate at a different rate depending on the configuration of the port.

34. The switch element of claim 19, wherein the port auto-negotiates with other ports, the rate at which the configurable port is operating.

35. A switch element for routing network frames, comprising:

a port that is configured to operate at one or more of a plurality of data transfer rates;

wherein a clock rate for one data transfer rate is not an even multiple of a clock rate for another data transfer rate at which the port is configured to operate;

wherein the port uses one interface to support one or more lanes for receiving and transferring frames at the plurality of data transfer rates; and

the one interface includes a plurality of selectable serial/de-serializer (SERDES); and

wherein a higher number of SERDES and a higher number of lanes are selected for a first data transfer rate, and a lower number of SERDES and a lower number of lanes are selected for supporting a second data transfer rate, where the first data transfer rate is higher than the second data transfer rate; and

wherein the switch element includes a clock configuration module for providing a clock signal that is based on a configured data transfer rate for the port.

36. The switch element of claim 35, wherein each of the plurality of lanes is configured to operate at a different rate depending on the configuration of the port.

37. The switch element of claim 35, wherein the data transfer rate is one or more of 1 G (gigabit per second);

2 G, 4 G, 8 G, 10 G or higher than 10 G.

38. The switch element of claim 35, wherein the port auto-negotiates the rate at which it is operating with other ports.