Method for Reducing Plasma Discharge Damage During Processing

• US 20090291547A1
• Filed: 05/22/2008
• Published: 11/26/2009
• Est. Priority Date: 05/22/2008
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Shroff, Mehul D., Schraub, David M., Legg, James D., Breeden, Terry A., Tian, Ruiqi
• Granted Patent: US 7,951,695 B2
• Time in Patent Office: Days
• US Class Current: 438/514
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26546 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional resist openings (119) formed over inactive areas (15) in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings (119) are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g., 152) for use in manufacturing the final structure.

Claims

1. A method for fabricating a semiconductor structure, comprising:

applying a layer of photoresist over a substrate to cover both an active circuit area and an inactive circuit area; and

patterning the layer of photoresist to define a first group of photoresist openings over the active circuit area and a second group of photoresist openings over the inactive circuit area, where the first group of photoresist openings and the second group of photoresist openings together define a total resist coverage percentage for the semiconductor structure that is at or below a predetermined threshold coverage level that is selected to reduce electrostatic discharge into the active circuit area through the first group of photoresist openings.

2. The method of claim 1, where patterning the layer of photoresist comprises patterning the layer of photoresist to form a first implant mask in which the first group of photoresist openings define a first group of implant substrate regions in the active circuit area to be implanted with ions having a first predetermined conductivity type, where the first implant mask includes the second group of photoresist openings to define a second group of implant substrate regions in the inactive circuit area to be implanted with ions having the first predetermined conductivity type.

3. The method of claim 2, further comprising implanting ions having the first predetermined conductivity type through the first and second groups of photoresist openings in the first implant mask and into the substrate, thereby forming the first group of implant substrate regions in the active circuit area and the second group of implant substrate regions in the inactive circuit area.

4. The method of claim 1, where patterning the layer of photoresist comprises patterning the layer of photoresist to form a first etch mask in which the first group of photoresist openings define a first group of etch openings in an underlying layer to be etched with a plasma-based etch process, where the first etch mask includes the second group of photoresist openings to define a second group of etch openings in the underlying layer to be etched with the plasma-based etch process.

5. The method of claim 4, further comprising applying the plasma-based etch process with the first etch mask in place over the underlying layer, thereby forming the first group of etch openings in the underlying layer over the active circuit area and the second group of etch openings in the underlying layer over the inactive circuit area.

6. The method of claim 5, where applying the plasma-based etch process exposes previously formed conductive tiling layers below the second group of etch openings in the underlying layer over the inactive circuit area such that the conductive tiling layers are disposed to direct charge from the inactive circuit area.

7. The method of claim 6, where the conductive tiling layers are formed from an aluminum or silicon based material.

8. The method of claim 1, where patterning the layer of photoresist comprises defining the first and second groups of photoresist openings so that the total resist coverage percentage for the semiconductor structure is at or below a predetermined threshold coverage level of between ninety and ninety-five percent.

9. The method of claim 1, where the first group of photoresist openings over the active circuit area are not alone sufficient to provide the predetermined threshold coverage level, and where the second group of photoresist openings over the inactive circuit area are required in combination with the first group of photoresist openings to provide the predetermined threshold coverage level.

10. A method for forming a semiconductor structure, comprising:

providing a semiconductor structure in which one or more active circuit areas and one or more inactive areas are formed;

depositing a photoresist layer over a coverage area of the semiconductor structure;

forming a plurality of openings in the photoresist layer over the active and inactive areas to expose at least a predetermined threshold percentage of the semiconductor structure in the coverage area, where the predetermined threshold percentage is selected to reduce electrostatic discharge through openings in the photoresist layer and into the one or more active circuit areas; and

performing a plasma-based process on the semiconductor structure such one or more openings formed over the one or more inactive areas define one or more charge dissipation structures for dissipating charge from the photoresist layer.

11. The method of claim 10, where performing a plasma-based process comprises performing a plasma-based etch of the photoresist layer.

12. The method of claim 10, where performing a plasma-based process comprises applying a plasma-based ash process to the photoresist layer.

13. The method of claim 10, where performing a plasma-based process comprises performing a plasma-based implantation process to implant impurities into the semiconductor structure through the plurality of openings.

14. The method of claim 10, where forming a plurality of openings in the photoresist layer comprises patterning the photoresist layer to form a patterned photoresist structure having a first group of photoresist openings over the one or more active circuit areas and a second group of photoresist openings over the one or more inactive areas.

15. The method of claim 14, where each of the second group of photoresist openings exposes a conductive layer, semiconductor layer or screen oxide layer in the semiconductor structure.

16. The method of claim 10, where forming a plurality of openings comprises:

forming a first plurality of openings in the photoresist over the active area which do not expose the predetermined threshold percentage of the semiconductor structure in the coverage area; and

forming a second plurality of openings in the photoresist over the inactive area such that the first and second plurality of openings in the photoresist together expose the predetermined threshold percentage of the semiconductor structure in the coverage area.

17. The method of claim 10, where forming a plurality of openings in the photoresist layer comprises patterning the photoresist layer to define a first group of photoresist openings over the one or more active circuit areas and a second group of photoresist openings over the one or more inactive areas, where the first and second groups of photoresist openings together expose at least a predetermined threshold percentage of five percent of the semiconductor structure in the coverage area when performing a relatively low energy plasma-based implantation process.

18. The method of claim 10, where forming a plurality of openings in the photoresist layer comprises patterning the photoresist layer to define a first group of photoresist openings over the one or more active circuit areas and a second group of photoresist openings over the one or more inactive areas, where the first and second groups of photoresist openings together expose at least a predetermined threshold percentage of ten percent of the semiconductor structure in the coverage area when performing a relatively high energy plasma-based implantation process.

19. A method for designing a patterned photoresist layer for at least a first circuit block of a wafer, comprising:

computing a coverage value for a mask layout used to pattern a photoresist layer on at least a first circuit block of a wafer based on an area computation for all openings defined in the mask layout; and

generating a modified mask layout to include one or more additional openings located over one or more inactive circuit areas and re-computing the coverage value for the modified mask layout based on an area computation for all openings defined in the mask layout until the coverage value is at or below a predetermined coverage threshold value.

20. The method of claim 19, further comprising iteratively repeating the computing and generating steps after reducing the predetermined coverage threshold value until a modified mask layout is generated that meets a predetermined design limit.

21. The method of claim 20, where the predetermined design limit comprises a layout constraint, an implant uniformity requirement, or a resist penetration requirement.

22. The method of claim 20, further comprising designing the patterned photoresist layer for a second circuit block of a wafer, comprising:

computing a second coverage value for the mask layout used to pattern the photoresist layer on the second circuit block of the wafer; and

generating a modified mask layout to include one or more additional openings located over one or more inactive circuit areas in the second circuit block and re-computing the second coverage value for the modified mask layout based on an area computation for all openings defined in the mask layout until the second coverage value is at or below a second predetermined coverage threshold value which is different from the first predetermined coverage threshold value.

23. The method of claim 22, where the first predetermined coverage threshold value is used to generate the modified mask layout for a digital circuit block, and where the second predetermined coverage threshold value is used to generate the modified mask layout for an analog circuit block, such that the second predetermined coverage threshold value is less than the first predetermined coverage threshold value.

24. The method of claim 19, further comprising manufacturing an integrated circuit using the modified mask layout which includes the one or more additional openings located over one or more inactive circuit areas.