RF TRANSCEIVER HAVING A T/R SWITCH CIRCUIT WITH HIGH POWER-HANDLING CAPABILITY

• US 20090291645A1
• Filed: 11/30/2008
• Published: 11/26/2009
• Est. Priority Date: 05/21/2008
• Status: Active Grant

• Current Assignee: Ralink Technology Corporation (MediaTek, Inc.)
• Original Assignee: Ralink Technology Corporation (MediaTek, Inc.)
• Inventors: Chu, Chun-Hsueh, Chen, Jiunn-Tsair
• Granted Patent: US 8,064,845 B2
• Time in Patent Office: Days
• US Class Current: 455/78
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A RF transceiver includes an antenna, a receiver, a baseband circuit, a transmitter, and a T/R switch circuit. The T/R switch circuit is used for coupling the antenna and the receiver or coupling the antenna and the transmitter. The T/R switch circuit is coupled to the baseband circuit so as to receive biases provided from the baseband circuit. The T/R switch circuit includes four transistors and a power detector. The power detector detects the power of the output signal of the T/R switch circuit, so that the baseband circuit can adjust biases provided to the T/R switch circuit according to the power of the output signal.

Claims

1. A T/R switch circuit for coupling a first node to a second node or a third node, comprising:

a first transistor, a source of the first transistor being coupled to the first node, a drain of the first transistor being coupled to the second node and receiving a first bias, a gate of the first transistor receiving a first control voltage;

a second transistor, a source of the second transistor being coupled to the first node, a drain of the second transistor being coupled to the third node and receiving the first bias, a gate of the second transistor receiving a second control voltage;

a third transistor, a source of the third transistor receiving a second bias, a drain of the third transistor being coupled to the second node and receiving the first bias, a gate of the third transistor receiving the second control voltage;

a fourth transistor, a source of the fourth transistor receiving the second bias, a drain of the fourth transistor being coupled to the third node and receiving the first bias, a gate of the fourth transistor receiving the first control voltage; and

a power detector for detecting power of output signals of the second node and the third node so as to adjust the first control voltage, the second control voltage, the first bias, and the second bias.

2. The T/R switch circuit of claim 1, wherein the first control voltage and the second control voltage are complementary voltages.

3. The T/R switch circuit of claim 1, wherein when the power of the output signals increases, the first bias and the second bias are increased.

4. The T/R switch circuit of claim 1, wherein the first node is coupled to an antenna, the second node is coupled to a transmitter, and the third node is coupled to a receiver.

5. The T/R switch circuit of claim 1, wherein the power detector transmits the power of the output signals to a baseband circuit so that the baseband circuit can adjust the first control voltage, the second control voltage, the first bias, and the second bias.

6. A RF transceiver, comprising:

an antenna for receiving or transmitting an analog signal;

a receiver for converting the analog signal to a digital signal;

a baseband circuit, being coupled to the receiver, for processing the digital signal;

a transmitter, being coupled to the baseband circuit, for converting the digital signal to the analog signal; and

a T/R switch circuit for coupling the antenna to the receiver or the transmitter, the T/R switch circuit being coupled to the baseband circuit for receiving biases provided by the baseband circuit.

7. The RF transceiver of claim 6, wherein the T/R switch circuit comprising:

a first transistor, a source of the first transistor being coupled to the first node, a drain of the first transistor being coupled to the second node and receiving a first bias, a gate of the first transistor receiving a first control voltage;

a second transistor, a source of the second transistor being coupled to the first node, a drain of the second transistor being coupled to the third node and receiving the first bias, a gate of the second transistor receiving a second control voltage;

a third transistor, a source of the third transistor receiving a second bias, a drain of the third transistor being coupled to the second node and receiving the first bias, a gate of the third transistor receiving the second control voltage;

a fourth transistor, a source of the fourth transistor receiving the second bias, a drain of the fourth transistor being coupled to the third node and receiving the first bias, a gate of the fourth transistor receiving the first control voltage; and

a power detector for detecting power of output signals of the second node and the third node so as to adjust the first control voltage, the second control voltage, the first bias, and the second bias.

8. The RF transceiver of claim 7, wherein the baseband circuit adjusts the first control voltage, the second control voltage, the first bias and the second bias according to the power of the analog signal.

9. The RF transceiver of claim 7, wherein the first control voltage and the second control voltage are complementary voltages.

10. The RF transceiver of claim 7, wherein when the power of the analog signal increases, the baseband circuit increases the first bias and the second bias.