Data processing apparatus and method for handling address translation for access requests issued by processing circuitry

• US 20090292899A1
• Filed: 05/21/2008
• Published: 11/26/2009
• Est. Priority Date: 05/21/2008
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: GRISENTHWAITE, Richard Roy, MANSELL, David Hennah
• Granted Patent: US 8,140,820 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, whilst also allowing certain problem cases to be handled correctly and in an efficient manner.

Claims

1. A data processing apparatus comprising:

processing circuitry for performing data processing operations;

a memory system for storing data for access by the processing circuitry when performing said data processing operations;

address translation circuitry, responsive to an access request issued by the processing circuitry and specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in said memory system corresponding to the virtual address;

a storage unit accessible by the address translation circuitry and having a plurality of entries, each entry storing address translation information for one or more virtual addresses, and each entry having a field which indicates whether the address translation information is consolidated address translation information enabling the address translation circuitry to generate the physical address, or is partial address translation information enabling the address translation circuitry to generate one of said at least one intermediate addresses;

responsive to the access request issued by the processing circuitry, the address translation circuitry referencing the storage unit to determine whether one of said entries provides address translation information for the specified virtual address;

if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is consolidated address translation information, the address translation circuitry producing the physical address directly from the consolidated address translation information; and

if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is partial address translation information, the address translation circuitry producing said one of said at least one intermediate addresses from the partial address translation information before performing the remainder of the multi-stage address translation process.

2. A data processing apparatus as claimed in claim 1, further comprising:

control circuitry for populating an entry in the storage unit with address translation information, the control circuitry when producing the address translation information checking if one or more predetermined conditions exist;

if said one or more predetermined conditions exist, the control circuitry producing said partial address translation information and setting the field to identify a stage of the multi-stage address translation process that will be reached by the address translation circuitry when using the partial address translation information; and

if said one or more predetermined conditions do not exist, the control circuitry producing said consolidated address translation information and setting the field to indicate that the address translation information is consolidated address translation information.

3. A data processing apparatus as claimed in claim 2, wherein the processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry, at least a final stage of the multi-stage address translation process employing address translation information controlled by the hypervisor software.

4. A data processing apparatus as claimed in claim 1 wherein for each stage of the multi-stage address translation process a page table is provided in said memory system, each page table containing a number of descriptors, each descriptor containing, for an associated address range, address translation information and access control information for the associated stage.

5. A data processing apparatus as claimed in claim 4, wherein for each entry of the storage unit storing partial address translation information, the entry further stores the access control information for each stage of the multi-stage address translation process.

6. A data processing apparatus as claimed in claim 2, wherein:

for each stage of the multi-stage address translation process a page table is provided in said memory system, each page table containing a number of descriptors, each descriptor containing, for an associated address range, address translation information and access control information for the associated stage; and

one of said one or more predetermined conditions checked by the control circuitry is whether an address range associated with the relevant descriptor in the page table for an earlier stage of the multi-stage address translation process is larger than an address range associated with the relevant descriptor in the page table for a later stage of the multi-stage address translation process.

7. A data processing apparatus as claimed in claim 2, wherein:

for each stage of the multi-stage address translation process a page table is provided in said memory system, each page table containing a number of descriptors, each descriptor containing, for an associated address range, address translation information and access control information for the associated stage; and

one of said one or more predetermined conditions checked by the control circuitry is whether the access control information associated with the relevant descriptor in the page table for an earlier stage of the multi-stage address translation process is more permissive than the access control information associated with the relevant descriptor in the page table for a later stage of the multi-stage address translation process.

8. A data processing apparatus as claimed in claim 1 wherein the multi-stage address translation process is a two stage process, a first stage causing the specified virtual address to be translated to a corresponding intermediate address, and a second stage causing the corresponding intermediate address to be translated to a corresponding physical address.

9. A data processing apparatus as claimed in claim 8, wherein:

if said one of said entries of the storage unit stores consolidated address translation information, that consolidated address translation information allows the address generation circuitry to directly generate the corresponding physical address from the specified virtual address; and

if said one of said entries of the storage unit stores partial address translation information, that partial address translation information allows the address generation circuitry to generate the corresponding intermediate address from the specified virtual address.

10. A data processing apparatus as claimed in claim 9, wherein

for both stages of the two-stage address translation process a page table is provided in said memory system, each page table containing a number of descriptors;

within a first page table each descriptor contains, for an associated virtual address range, address translation information and access control information for the first stage;

within a second page table each descriptor contains, for an associated intermediate address range, address translation information and access control information for the second stage; and

if said one of the entries of the storage unit stores partial address translation information, the address translation circuitry uses the partial address translation information to generate the corresponding intermediate address from the specified virtual address, and then references the second page table to complete the two-stage address translation process.

11. A data processing apparatus as claimed in claim 1, wherein the storage unit is a translation lookaside buffer (TLB).

12. A data processing apparatus as claimed in claim 11, further comprising a micro-TLB for storing address translation information used by the address translation circuitry for a number of previous access requests, and the address translation circuitry being arranged on receipt of said access request to only reference the TLB if the required address translation information is not present in the micro-TLB.

13. A data processing apparatus as claimed in claim 12, wherein whenever any entry in the TLB is invalidated, all address translation information in the entire micro-TLB is invalidated.

14. A data processing apparatus as claimed in claim 12, wherein the micro-TLB is arranged to store only consolidated address translation information.

15. A data processing apparatus as claimed in claim 12, wherein the micro-TLB is arranged to store both consolidated address translation information and partial address translation information, for any partial address translation information stored in the micro-TLB, the micro-TLB also storing access control information associated with each stage of the multi-stage address translation process.

16. A data processing apparatus as claimed in claim 2, wherein said control circuitry comprises page table access circuitry for determining the address translation information to be used to populate an entry of the storage unit by accessing page tables provided in said memory system, a page table being provided for each stage of the multi-stage address translation process.

17. A data processing apparatus as claimed in claim 16, wherein said page table access circuitry contains an additional storage unit for caching address translation information obtained from descriptors provided within at least the page table associated with a final stage of the multi-stage address translation process.

18. A method of handling address translation for access requests issued by processing circuitry in order to access data in a memory system, comprising the steps of:

responsive to an access request issued by the processing circuitry and specifying a virtual address, employing address translation circuitry to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in said memory system corresponding to the virtual address;

providing a storage unit accessible by the address translation circuitry and having a plurality of entries, each entry storing address translation information for one or more virtual addresses, and providing each entry with a field which indicates whether the address translation information is consolidated address translation information enabling the address translation circuitry to generate the physical address, or is partial address translation information enabling the address translation circuitry to generate one of said at least one-intermediate addresses;

responsive to the access request issued by the processing circuitry, the address translation circuitry performing the steps of;

referencing the storage unit to determine whether one of said entries provides address translation information for the specified virtual address;

if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is consolidated address translation information, producing the physical address directly from the consolidated address translation information; and

if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is partial address translation information, producing said one of said at least one intermediate addresses from the partial address translation information before performing the remainder of the multi-stage address translation process.

19. A data processing apparatus comprising:

processing means for performing data processing operations;

memory means for storing data for access by the processing means when performing said data processing operations;

address translation means, responsive to an access request issued by the processing means and specifying a virtual address, for performing a multi-stage address translation process to produce, via at least one intermediate address, a physical address in said memory means corresponding to the virtual address;

a storage means accessible by the address translation means and having a plurality of entries, each entry for storing address translation information for one or more virtual addresses, and each entry having a field for indicating whether the address translation information is consolidated address translation information enabling the address translation circuitry to generate the physical address, or is partial address translation information enabling the address translation circuitry to generate one of said at least one intermediate addresses;

responsive to the access request issued by the processing means, the address translation means for referencing the storage means to determine whether one of said entries provides address translation information for the specified virtual address;

if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is consolidated address translation information, the address translation means for producing the physical address directly from the consolidated address translation information; and

if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is partial address translation information, the address translation means for producing said one of said at least one intermediate addresses from the partial address translation information before performing the remainder of the multi-stage address translation process.