Hard Component Failure Detection and Correction
First Claim
1. A memory controller comprising:
- a check bit encoder circuit coupled to receive a data block to be written to memory, wherein the check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits; and
a check/correct circuit coupled to receive an encoded data block read from the memory, the check/correct circuit configured to detect an error in the encoded data block responsive to the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block, and wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the first plurality of check bits covers a respective row of the array, and wherein the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits, and wherein a presence of more than one binary one in the first syndrome indicates a multi-bit error; and
a hard failure detection circuit coupled to the check/correct circuit wherein, responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.
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Accused Products
Abstract
In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled to the check/correct circuit. The check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits. The check/correct circuit is configured to detect an error in the encoded data block responsive to the first check bits, the second check bits, and the data block within the encoded data block, which is logically arranged as an array of R rows and N columns, wherein R and N are positive integers. Each of the first check bits covers a respective row of the array, and the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits. A presence of more than one binary one in the first syndrome indicates a multi-bit error. Responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.
35 Citations
21 Claims
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1. A memory controller comprising:
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a check bit encoder circuit coupled to receive a data block to be written to memory, wherein the check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits; and a check/correct circuit coupled to receive an encoded data block read from the memory, the check/correct circuit configured to detect an error in the encoded data block responsive to the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block, and wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the first plurality of check bits covers a respective row of the array, and wherein the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits, and wherein a presence of more than one binary one in the first syndrome indicates a multi-bit error; and a hard failure detection circuit coupled to the check/correct circuit wherein, responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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reading an encoded data block from memory, wherein the encoded data block comprises a data block, a first plurality of check bits, and a second plurality of check bits; detecting an error in the encoded data block responsive to the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block, wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the first plurality of check bits covers a respective row of the array, and wherein detecting the error comprises generating a first syndrome corresponding to the first plurality of check bits, and wherein a presence of more than one binary one in the first syndrome indicates a multi-bit error; and responsive to detecting the multi-bit error, identifying a hard failure in the memory by performing a plurality of memory read/write operations to the memory locations in which the encoded data block is stored. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An apparatus comprising:
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a check bit encoder circuit coupled to receive a data block, wherein the check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits; and a check/correct circuit coupled to receive an encoded data block, the check/correct circuit configured to detect an error in data from one of a plurality of components and correct the error using the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block; wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein the first plurality of check bits form a first column of the array, and wherein each of the first plurality of check bits covers a row of the array, and wherein the second plurality of check bits are stored in a second column of the array and are defined to cover bits in the array according to a plurality of check vectors, each of the plurality of check vectors corresponding to a different bit in the array, and each of the plurality of check vectors is an element of a Galois Field (GF(2X)), and wherein X is a positive integer equal to a number of the second plurality of bits, and wherein the plurality of check vectors are derived from a plurality of unique elements of GF(2X), each of the plurality of unique elements corresponding to a different column of the array, and wherein each of the plurality of unique elements includes at least one non-zero bit, including the element corresponding to the first column of the array, and wherein the check vector in row Z of the column is the product, in GF(2X) of the unique element for that column and alphaZ, wherein alpha is a primitive element of GF(2X). - View Dependent Claims (20, 21)
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Specification