Thin film transistor, method of manufacturing the same and flat panel display device having the same

• US 20090294772A1
• Filed: 01/09/2009
• Published: 12/03/2009
• Est. Priority Date: 05/30/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yang, Hui-Won, Mo, Yeon-Gon, Jeong, Jae-Kyeong, Kim, Kwang-Suk, Jeong, Jong-Han
• Granted Patent: US 7,994,510 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A thin film transistor is provided having an oxide semiconductor as an active layer, a method of manufacturing the thin film transistor and a flat panel display device having the thin film transistor. The thin film transistor includes: a gate electrode formed on a substrate; an oxide semiconductor layer isolated from the gate electrode by a gate insulating layer and including channel, source and drain regions; source and drain electrodes coupled to the source and drain regions, respectively; and an ohmic contact layer interposed between the source and drain regions and the source and drain electrodes. In the TFT, the ohmic contact layer is formed with the oxide semiconductor layer having a carrier concentration higher than those of the source and drain regions.

Claims

1. A thin film transistor (TFT), comprising:

a substrate;

a gate electrode formed on the substrate;

an oxide semiconductor layer isolated from the gate electrode by a gate insulating layer and including channel, source and drain regions;

source and drain electrodes coupled to the source and drain regions, respectively; and

an ohmic contact layer interposed between the source and drain regions and the source and drain electrodes,

the ohmic contact layer being formed with the oxide semiconductor layer having a carrier concentration higher than those of the source and drain regions.

2. The TFT as claimed in claim 1, wherein the oxide semiconductor layer and the ohmic contact layer comprise oxide zinc (ZnO) as a main component.

3. The TFT as claimed in claim 2, wherein the oxide semiconductor layer and the ohmic contact layer are doped with at least one ion of indium (In), gallium (Ga) and stannum (Sn).

4. The TFT as claimed in claim 1, wherein the carrier concentration of the oxide semiconductor layer is 1e+13 to 1e+17#/cm³, and the carrier concentration of the ohmic contact layer is 1e+19 to 1e+21#/cm³.

5. A method of manufacturing a TFT, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the substrate having the gate electrode;

forming an oxide semiconductor layer including channel, source and drain regions on the gate insulating layer so that an ohmic contact layer having a carrier concentration higher than those of the source and drain regions is formed on a surface of the oxide semiconductor layer;

forming source and drain electrodes respectively coupled to the source and drain regions through the ohmic contact layer; and

removing the ohmic contact layer interposed between the source and drain electrodes.

6. The method as claimed in claim 5, wherein the oxide semiconductor layer is formed of zinc oxide (ZnO).

7. The method as claimed in claim 6, wherein at least one ion of indium (In), gallium (Ga) and stannum (Sn) is doped into the oxide semiconductor layer.

8. The method as claimed in claim 5, wherein the ohmic contact layer is formed by decreasing oxygen partial pressure in the process of forming the oxide semiconductor layer.

9. The method as claimed in claim 5, wherein the ohmic contact layer is formed by performing plasma treatment with respect to the surface of the oxide semiconductor layer.

10. The method as claimed in claim 5, wherein the carrier concentration of the oxide semiconductor layer is 1e+13 to 1e+17#/cm³, and the carrier concentration of the ohmic contact layer is 1e+19 to 1e+21#/cm³.

11. A flat panel display device having a TFT, comprising:

a first substrate having a plurality of pixels defined by a plurality of first and second conductive lines, a TFT controlling a signal supplied to each of the pixels, and a first electrode coupled to the TFT;

a second substrate having a second electrode; and

a liquid crystal layer injected into a sealed space between the first and second electrodes, the TFT comprising;

a gate electrode formed on the first substrate;

an oxide semiconductor layer isolated from the gate electrode by a gate insulating layer and including channel, source and drain regions;

source and drain electrodes coupled to the source and drain regions, respectively; and

an ohmic contact layer interposed between the source and drain regions and the source and drain electrodes,

the ohmic contact layer being formed with the oxide semiconductor layer having a carrier concentration higher than those of the source and drain regions.

12. The flat panel display device as claimed in claim 11, wherein the oxide semiconductor layer and the ohmic contact layer comprise oxide zinc (ZnO) as a main component.

13. The flat panel display device as claimed in claim 12, wherein the oxide semiconductor layer and the ohmic contact layer are doped with at least one ion of indium (In), gallium (Ga) and stannum (Sn).

14. The flat panel display device as claimed in claim 11, wherein the carrier concentration of the oxide semiconductor layer is 1e+13 to 1e+17#/cm³, and the carrier concentration of the ohmic contact layer is 1e+19 to 1e+21#/cm³.

15. A flat panel display device having a TFT, comprising:

a first substrate having an organic light emitting device including a first electrode, an organic thin film layer and a second electrode, and a TFT controlling an operation of the organic light emitting device; and

a second substrate disposed opposite to the first substrate,

the TFT comprising;

a gate electrode formed on the first substrate;

an oxide semiconductor layer isolated from the gate electrode by a gate insulating layer and including channel, source and drain regions;

source and drain electrodes coupled to the source and drain regions, respectively; and

an ohmic contact layer interposed between the source and drain regions and the source and drain electrodes,

the ohmic contact layer being formed with the oxide semiconductor layer having a carrier concentration higher than those of the source and drain regions.

16. The flat panel display device as claimed in claim 15, wherein the oxide semiconductor layer and the ohmic contact layer comprise oxide zinc (ZnO) as a main component.

17. The flat panel display device as claimed in claim 16, wherein the oxide semiconductor layer and the ohmic contact layer are doped with at least one ion of indium (In), gallium (Ga) and stannum (Sn).

18. The flat panel display device as claimed in claim 16, wherein the carrier concentration of the oxide semiconductor layer is 1e+13 to 1e+17#/cm³, and the carrier concentration of the ohmic contact layer is 1e+19 to 1e+21#/cm³.