RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION

• US 20090294839A1
• Filed: 05/30/2008
• Published: 12/03/2009
• Est. Priority Date: 05/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Dewey, Gilbert, Doyle, Brian S., Pillarisetty, Ravi
• Granted Patent: US 7,800,166 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Claims

1. A method comprising:

forming a first sacrificial gate structure on a first fin, the first fin being coupled with a semiconductor substrate;

removing the first sacrificial gate structure to expose the first fin;

recessing a channel structure into the first fin; and

forming a first gate structure of a recessed channel array transistor (RCAT) on the recessed channel structure.

2. A method according to claim 1 further comprising:

forming a second sacrificial gate structure on a second fin, the second fin being coupled with the semiconductor substrate, wherein forming the second sacrificial gate structure on the second fin occurs simultaneously with forming the first sacrificial gate structure on the first fin;

removing the second sacrificial gate structure to expose the second fin wherein removing the second sacrificial gate structure occurs simultaneously with removing the first sacrificial gate structure;

protecting the second fin such that the second fin remains after recessing the channel structure into the first fin; and

forming a second gate structure of a multi-gate transistor on the second fin.

3. A method according to claim 2 wherein recessing the channel structure into the first fin comprises:

etching away the material of the first fin to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor wherein increasing the depth reduces short channel effects in the RCAT by increasing the effective gate length of the first gate structure.

4. A method according to claim 2 wherein forming the first gate structure of the RCAT comprises forming the first gate structure having a first gate width and wherein forming the second gate structure of the multi-gate transistor comprises forming a second gate structure having a second gate width, wherein the first gate width is greater than about two times the second gate width.

5. A method according to claim 2 wherein the RCAT comprises a memory device having a first current leakage characteristic and the multi-gate transistor comprises a logic device having a second current leakage characteristic wherein the first current leakage characteristic is less than about one thousand times smaller than the second current leakage characteristic.

6. A method according to claim 1 wherein forming the first sacrificial gate structure on the first fin comprises depositing a sacrificial gate dielectric to the first fin and depositing a sacrificial gate electrode comprising polysilicon to the sacrificial gate dielectric, and wherein removing the first sacrificial gate structure to expose the first fin comprises etching to remove the sacrificial gate structure.

7. A method according to claim 1 wherein forming the first gate structure of the recessed channel array transistor (RCAT) on the recessed channel structure comprises:

depositing a gate dielectric to the recessed channel structure, the gate dielectric comprising a dielectric constant, k, that is greater than about 4; and

depositing a gate electrode to the gate dielectric, the gate electrode comprising a bandgap energy between about 4.1 electron volts (eV) and about 4.9 eV.

8. An apparatus comprising:

a semiconductor substrate;

a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region; and

a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

9. An apparatus according to claim 8 further comprising:

a second fin coupled with the semiconductor substrate, the second fin comprising a second source region, a second drain region, and a second gate region wherein the second gate region is disposed between the second source region and the second drain region; and

a second gate structure of a multi-gate transistor formed on the second gate region of the second fin wherein the multi-gate transistor comprises a logic device and wherein the RCAT comprises a memory device.

10. An apparatus according to claim 9 wherein the first gate structure of the RCAT comprises a first gate width and wherein the second gate structure of the multi-gate transistor comprises a second gate width wherein the first gate width is greater than about two times the second gate width.

11. An apparatus according to claim 9 wherein the first gate structure of the RCAT is further formed by recessing the channel structure to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor.

12. An apparatus according to claim 9 wherein the RCAT comprises a first gate leakage current and the multi-gate transistor comprises a second gate leakage current wherein the first gate leakage current is less than about one thousand times smaller than the second gate leakage current.

13. An apparatus according to claim 8 wherein the semiconductor substrate comprises silicon, the recessed channel structure comprises silicon, and wherein the first gate structure comprises:

a gate dielectric coupled with the recessed channel structure, the gate dielectric comprising a dielectric constant, k, greater than about 4; and

a gate electrode coupled with the gate dielectric, the gate electrode comprising a bandgap energy between about 4.1 electron volts (eV) and about 4.9 eV.

14. An apparatus according to claim 8 further comprising:

a dielectric material coupled with the first source region and the first drain region of the first fin and also coupled with the semiconductor substrate, the recessed channel structure, and the first gate structure.

15. An apparatus comprising:

a semiconductor substrate;

a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region;

a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region;

a second fin coupled with the semiconductor substrate, the second fin comprising a second source region, a second drain region, and a second gate region wherein the second gate region is disposed between the second source region and the second drain region; and

a second gate structure of a multi-gate transistor formed on the second gate region of the second fin wherein the multi-gate transistor comprises a logic device and wherein the RCAT comprises a memory device.

16. An apparatus according to claim 15 wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

17. An apparatus according to claim 16 wherein the first gate structure of the RCAT is further formed by recessing the channel structure to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor.

18. An apparatus according to claim 15 wherein the first gate structure of the RCAT comprises a first gate width and wherein the second gate structure of the multi-gate transistor comprises a second gate width wherein the first gate width is greater than about two times the second gate width.

19. A system according to claim 15 wherein the RCAT comprises a first gate leakage current and the multi-gate transistor comprises a second gate leakage current wherein the first gate leakage current is less than about one thousand times smaller than the second gate leakage current.

20. A system according to claim 15 wherein the semiconductor substrate and the recessed channel structure comprise silicon and wherein the first gate structure comprises:

a gate dielectric coupled with the recessed channel structure, the gate dielectric comprising a dielectric constant, k, greater than about 4; and

a gate electrode coupled with the gate dielectric, the gate electrode comprising a bandgap energy between about 4.1 electron volts (eV) and about 4.9 eV.