INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20090294845A1
• Filed: 08/11/2009
• Published: 12/03/2009
• Est. Priority Date: 02/19/2001
• Status: Active Grant

• Current Assignee: Renesas Semiconductor Package & Test Solutions Co., Ltd. (Renesas Electronics Corporation)
• Original Assignee: Hitachi TOBU Semiconductor Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: INAGAWA, HIROSHI, Oishi, Kentaro, Machida, Nobuo
• Granted Patent: US 7,843,001 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Claims

1-14. -14. (canceled)

15. An insulated-gate type semiconductor device having a longitudinal structure, comprising:

a semiconductor main body indicative of a first conductivity type;

a first semiconductor region indicative of a second conductivity type, which is formed in said semiconductor main body;

a second semiconductor region indicative of the first conductivity type, which is formed in said first semiconductor region; and

a trench gate which is reached from a major surface of said second semiconductor region to the region of said semiconductor main body;

wherein;

a portion of a gate pillar which is made of both said trench gate and an insulating film for covering an upper surface of said trench gate exceeds and is projected from the major surface of said second semiconductor region;

a side wall spacer is provided on a side wall of said projected gate pillar; and

a source electrode connected to said semiconductor region is provided on a contact region defined by said side wall spacer.

17. An insulated-gate type semiconductor device as claimed in claim 15 wherein:

said side wall is formed via a thermal oxidation film which is formed on a surface of the projected portion of said trench gate.

16. An insulated-gate type semiconductor device having a longitudinal structure, comprising:

a semiconductor main body indicative of a first conductivity type;

a first semiconductor region indicative of a second conductivity type, which is formed in said semiconductor main body;

a second semiconductor region indicative of the first conductivity type, which is formed in said first semiconductor region; and

a trench gate which is reached from a major surface of said second semiconductor region to the region of said semiconductor main body;

wherein;

a portion of said trench gate exceeds and is projected from the major surface of said second semiconductor region;

a side wall spacer is provided on both said projected trench gate and a side wall of an insulating film for covering an upper surface of said trench gate; and

a source electrode connected to said semiconductor region is provided in a contact hole defined by said side wall spacer.

18. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:

a step of forming a first semiconductor region within said semiconductor substrate;

a step of forming a trench in said semiconductor substrate in such a manner that said trench penetrates said first semiconductor forming region;

a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within said trench;

a step in which the trench where said gate insulating film is formed by a gate pillar made of both said gate-purpose conductive layer and a cap insulating film for capping an upper surface of said gate-purpose conductive layer, and a portion of said gate pillar is projected from the major surface of said semiconductor substrate;

a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trench;

a step of forming a side wall spacer on both said projected conductive layer and an insulating film for covering an upper surface of said projected conductive layer; and

a step of forming said source-purpose conductive layer in a source contact region defined by said side wall spacer.

19. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:

a step of forming a first semiconductor region within said semiconductor substrate;

a step of forming a plurality of trenches in said semiconductor substrate in such a manner that said trenches penetrate said first semiconductor forming region;

a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within each of said trenches;

a step in which each of said trenches where said gate insulating film is formed is embedded, and a portion of said gate-purpose conductive layer which is projected to the major surface of the semiconductor substrate is formed;

a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trenches;

a step of forming a side wall spacer on both said projected conductive layer and an insulating film for covering an upper surface of said projected conductive layer;

a step of forming a contact hole in a source contact region defined by said side wall spacer; and

a step of forming said source-purpose conductive layer in said contact hole.

20. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:

a step of forming a first semiconductor region within said semiconductor substrate;

a step of forming a trench in said semiconductor substrate in such a manner that said trench penetrates said first semiconductor forming region;

a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within said trench;

a step in which the trench where said gate insulating film is formed by a gate pillar made of both said conductive layer for said gate and a cap insulating film for capping an upper surface of said conductive layer for said gate, and a portion of said gate pillar is projected from the major surface of said semiconductor substrate;

a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trench;

a step of forming a side wall spacer on both said projected conductive layer and an insulating film for covering an upper surface of said projected conductive layer;

a step of forming a contact hole in said second semiconductor region, while said side wall spacer is employed as a mask;

a step in which after said contact hole has been formed, the side wall spacer is moved backwardly by way of an etching back operation so as to expose a surface of the semiconductor substrate of said second semiconductor region; and

a step of forming said source-purpose conductive layer within both the exposed surface portion of the semiconductor substrate of said second semiconductor region and also said contact hole.