FIELD EFFECT STRUCTURE AND METHOD INCLUDING SPACER SHAPED METAL GATE WITH ASYMMETRIC SOURCE AND DRAIN REGIONS

• US 20090294873A1
• Filed: 05/29/2008
• Published: 12/03/2009
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Zhengwen, Zhu, Huilong
• Granted Patent: US 7,768,006 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device, such as a field effect transistor, that includes a spacer shaped metal gate located over a channel within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. Within the semiconductor structure, the plurality of source and drain regions is asymmetric with respect to the spacer shaped metal gate. The particular semiconductor structure may be fabricated using a self aligned dummy gate method that uses a portion of a spacer as a self alignment feature when forming the spacer shaped metal gate, which may have a sub-lithographic linewidth.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate that includes a channel region;

a plurality of source regions and drain regions located within the semiconductor substrate and separated by the channel region; and

a metal gate that has a spacer shape located over the channel region, where the plurality of source regions and drain regions is asymmetric with respect to the metal gate.

2. The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a bulk semiconductor substrate.

3. The semiconductor substrate of claim 1 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.

4. The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a hybrid orientation substrate.

5. The semiconductor structure of claim 1 wherein the plurality of source regions and drain regions is asymmetric in shape with respect to the metal gate.

6. The semiconductor structure of claim 1 wherein the plurality of source regions and drain regions is asymmetric in location with respect to the metal gate.

7. The semiconductor structure of claim 1 wherein the plurality of source regions and drain regions is asymmetric in dopant profile with respect to the metal gate.

8. The semiconductor structure of claim 1 wherein the metal gate comprises a metal material selected from the group consisting of metals, metal alloys and metal nitrides.

9. The semiconductor structure of claim 1 further comprising a plurality of silicide layers located upon the plurality of source regions and drain regions.

10. The semiconductor structure of claim 9 wherein the plurality of silicide layers is spaced equally from the metal gate.

11. The semiconductor structure of claim 1 further comprising a gate dielectric located interposed between the metal gate and the channel, the gate dielectric comprising a gate dielectric material having a dielectric constant greater than 20.

12. A semiconductor structure comprising:

a semiconductor substrate that includes a channel region;

a plurality of source regions and drain regions located within the semiconductor substrate and separated by the channel region;

a metal gate that has a spacer shape located over the channel region; and

a spacer located adjacent opposite sidewalls of the metal gate, where the plurality of source regions and drain regions is asymmetric with respect to the metal gate.

13. The semiconductor structure of claim 12 further comprising a plurality of silicide layers located upon the plurality of source regions and drain regions.

14. The semiconductor structure of claim 13 wherein the plurality of silicide layers is equally spaced from the metal gate.

15. The semiconductor structure of claim 12 further comprising a gate dielectric located interposed between the metal gate and the channel, the gate dielectric comprising a gate dielectric material having a dielectric constant greater than 20.

16. A method for fabricating a semiconductor structure comprising:

forming a dummy gate over a semiconductor substrate;

forming a spacer adjacent the dummy gate;

forming a plurality of source regions and drain regions into the semiconductor substrate that are separated by a channel within the semiconductor substrate while using, at least in part, the gate and the spacer as a mask;

stripping a portion of the spacer, and all of the dummy gate, from over the semiconductor substrate to leave a remaining portion of the spacer over the semiconductor substrate; and

forming a spacer shaped metal gate over the channel and asymmetric with respect to the plurality of source regions and drain regions while using the remaining portion of the spacer as a self-alignment feature.

17. The method of claim 16 wherein the stripping the portion of the spacer uses a selective masking and etch method.

18. The method of claim 16 wherein the stripping the portion of the spacer uses a selective ion implantation and etch method.

19. The method of claim 16 wherein the forming the spacer shaped metal gate uses an anisotropic etch method.

20. The method of claim 19 wherein the anisotropic etch method provides the spacer shaped metal gate of sub-lithographic linewidth.