MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES

• US 20090294898A1
• Filed: 03/10/2009
• Published: 12/03/2009
• Est. Priority Date: 05/30/2008
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Werner, Thomas, Frohberg, Kai, Feustel, Frank
• Application Number:
  US12/400,983
• Publication Number:
  US 20090294898A1
• Time in Patent Office: Days
• US Class Current: 257/522
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.

Claims

1. A method, comprising:

forming a recess in a dielectric material of a metallization layer of a semiconductor device, said recess extending between two neighboring metal regions formed in said dielectric material;

forming a spacer element on sidewalls of said recess; and

forming a gap between said two neighboring metal regions by using said spacer element as an etch mask.

2. The method of claim 1, further comprising forming a cap layer above said gap so as to maintain at least a portion of said gap as a dielectric barrier between said two neighboring metal regions.

3. The method of claim 1, wherein forming said recess comprises performing an etch process to remove material of said dielectric material selectively to said two neighboring metal regions.

4. The method of claim 1, further comprising providing a first etch control layer in said dielectric material to adjust a depth of said recess.

5. The method of claim 1, further comprising providing a second etch control layer in said dielectric material to adjust a depth of said gap.

6. The method of claim 1, further comprising removing said spacer element after forming said gap.

7. The method of claim 1, further comprising forming a mask to expose a first device region and cover a second device region, wherein said first device region comprises a space between said two neighboring metal regions.

8. The method of claim 1, wherein forming said spacer element comprises forming an etch stop layer above said dielectric material after forming said recess and forming a spacer layer on said etch stop layer.

9. The method of claim 8, wherein said etch stop layer comprises a barrier material for suppressing metal diffusion.

10. The method of claim 8, wherein said etch stop layer comprises a conductive material.

11. The method of claim 10, further comprising removing portions of said etch stop layer not covered by said spacer element.

12. The method of claim 1, wherein forming said spacer element comprises depositing a conductive material and anisotropically etching said conductive material so as to obtain said spacer element.

13. A method comprising:

forming a recess between a first metal line and a second metal line, said first and second metal lines formed in a dielectric material of a metallization layer of a microstructure device;

defining a reduced width of said recess by depositing a spacer layer into said recess; and

forming a gap between said first and second metal lines on the basis of said reduced width.

14. The method of claim 13, wherein defining said reduced width comprises forming a spacer element in said recess.

15. The method of claim 13, wherein forming said gap comprises performing an anisotropic etch process and using said spacer layer as an etch mask.

16. The method of claim 15, wherein said performing said anisotropic etch process comprises removing material of said spacer layer and said dielectric material of said metallization layer in a common process.

17. The method of claim 14, further comprising removing said spacer element after forming said gap.

18. The method of claim 13, further comprising covering a portion of said metallization layer by an etch mask and forming said gap in a non-covered portion of said metallization layer.

19. The method of claim 13, further comprising depositing a dielectric cap layer above said metallization layer after forming said gap to maintain at least a portion of said gap for reducing capacitive coupling between said first and second metal lines.

20. A microstructure device, comprising:

a first metal line formed in a dielectric material of a metallization layer;

a second metal line formed in the dielectric material of said metallization layer laterally adjacent to said first metal line;

an air gap located in said dielectric material between said first and second metal lines;

a first spacer element formed at a portion of a first sidewall of said first metal line that faces a second sidewall of said second metal line; and

a second spacer element formed at a portion of said second sidewall of said second metal line.

21. The device of claim 20, wherein said first and second spacer elements do not extend along the entire thickness of said first and second metal lines.

22. The device of claim 21, wherein said first and second spacer elements extend from a height level corresponding to a top surface of said first and second metal lines to less than half a thickness of said first and second metal lines.

23. The device of claim 20, further comprising at least some metal lines that are formed in said dielectric material of said metallization layer without an adjacent air gap.

24. The device of claim 20, further comprising transistor elements having a gate length of approximately 30 nm or less.

25. The device of claim 24, wherein a lateral size of said air gap is less than a gate length of said transistor elements.