Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material

• US 20090294914A1
• Filed: 05/27/2008
• Published: 12/03/2009
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Chua, Linda Pei Ee, Do, Byung Tai, Pagaila, Reza A.
• Granted Patent: US 7,741,156 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a first semiconductor wafer having a plurality of semiconductor die, each semiconductor die having a contact pad;

creating a gap between the semiconductor die, the gap having sufficient width to form a conductive via within the gap;

depositing an insulating material in the gap;

forming a conductive layer over the semiconductor die, the conductive layer being electrically connected to the contact pad of the semiconductor die;

removing a portion of the insulating material to form a through hole via (THV);

conforming a conductive lining in the THV;

disposing a solder material above the conductive lining of the THV;

reflowing the solder material to form the conductive via within the gap, the conductive via being electrically connected to the conductive layer; and

singulating the first semiconductor wafer through the gap to separate the semiconductor die.

2. The method of claim 1, further including:

stacking a second semiconductor wafer having a plurality of semiconductor die over the first semiconductor wafer, the second semiconductor wafer having a gap between the semiconductor die;

forming a conductive via in the gap of the second semiconductor wafer; and

aligning the conductive via in the first semiconductor wafer to the conductive via in the second semiconductor wafer.

3. The method of claim 1, further including:

stacking a plurality of semiconductor die; and

electrically interconnecting the plurality of semiconductor die through the conductive vias.

4. The method of claim 3, wherein the plurality of semiconductor die are stacked in a pyramid arrangement.

5. The method of claim 3, wherein the plurality of semiconductor die are stacked in a face-to-face, back-to-back, or face-to-back arrangement.

6. The method of claim 3, wherein the plurality of semiconductor die are substantially the same size.

7. The method of claim 1, further including forming a through silicon via under the contact pad of the semiconductor die.

8. The method of claim 1, further including depositing the insulating material on a backside of the semiconductor die opposite the contact pad.

9. A method of making a semiconductor device, comprising:

providing a first semiconductor wafer having a plurality of semiconductor die;

creating a gap between the semiconductor die;

depositing an insulating material in the gap;

removing a portion of the insulating material to form a through hole via (THV);

conforming a conductive lining in the THV;

disposing a conductive material above the conductive lining of the THV;

reflowing the conductive material to form a conductive via within the gap; and

singulating the first semiconductor wafer through the gap to separate the semiconductor die.

10. The method of claim 9, further including forming a conductive layer over the semiconductor die, the conductive layer being electrically connected to a contact pad of the semiconductor die.

11. The method of claim 9, further including:

stacking a second semiconductor wafer having a plurality of semiconductor die over the first semiconductor wafer, the second semiconductor wafer having a gap between the semiconductor die;

forming a conductive via in the gap of the second semiconductor wafer; and

aligning the conductive via in the first semiconductor wafer to the conductive via in the second semiconductor wafer.

12. The method of claim 9, further including:

stacking a plurality of semiconductor die; and

electrically interconnecting the plurality of semiconductor die through the conductive vias.

13. The method of claim 12, wherein the plurality of semiconductor die are stacked in a face-to-face, back-to-back, or face-to-back arrangement.

14. The method of claim 9, further including forming a through silicon via under a contact pad of the semiconductor die.

15. A method of making a semiconductor device, comprising:

creating a gap between a plurality of semiconductor die;

depositing an insulating material in the gap;

removing a portion of the insulating material to form a through hole via (THV);

conforming a conductive lining in the THV;

disposing a conductive material above the conductive lining of the THV; and

reflowing the conductive material to form a conductive via within the gap.

16. The method of claim 15, further including forming a conductive layer over the semiconductor die, the conductive layer being electrically connected to a contact pad of the semiconductor die.

17. The method of claim 15, further including:

stacking a plurality of semiconductor die; and

electrically interconnecting the plurality of semiconductor die through the conductive vias.

18. The method of claim 17, wherein the plurality of semiconductor die are stacked in a pyramid arrangement.

19. The method of claim 17, wherein the plurality of semiconductor die are stacked in a face-to-face, back-to-back, or face-to-back arrangement.

20. The method of claim 15, further including forming a through silicon via under a contact pad of the semiconductor die.

21. A semiconductor device, comprising:

a semiconductor die having a peripheral region; and

a conductive via formed in a though hole via (THV) in insulating material in the peripheral region, the conductive via having a conductive lining conforming to the THV and a conductive material filling the lining.

22. The semiconductor device of claim 21, further including a conductive layer formed over the semiconductor die, the conductive layer being electrically connected to a contact pad of the semiconductor die.

23. The semiconductor device of claim 21, wherein the plurality of semiconductor die is stacked and electrically interconnected by the conductive via.

24. The semiconductor device of claim 23, wherein the plurality of semiconductor die are stacked in a face-to-face, back-to-back, or face-to-back arrangement.

25. The semiconductor device of claim 23, further including a through silicon via formed under a contact pad of the semiconductor die.