SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20090294951A1
• Filed: 01/15/2008
• Published: 12/03/2009
• Est. Priority Date: 01/29/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Kayashima, Yuji, Yamamichi, Shintaro, Funaya, Takuo, Murai, Hideya, Maeda, Takehiko
• Granted Patent: US 8,043,953 B2
• Time in Patent Office: Days
• US Class Current: 257/693
• CPC Class Codes: B23K 26/389 of fluid openings, e.g. nozzles, jets laser machining of inkjet nozzles B41J2/1634
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.

Claims

1. A semiconductor device, comprising:

a individually divided LSI chip including an externally connected pad;

an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in a position corresponding to the externally connected pad; and

a wiring layer extending along the insulating layer through the via hole to the externally connected pad,

wherein at least part of the via hole is formed by irradiating the insulating layer with laser light, and

the externally connected pad includes the same surface as a reference surface of the LSI chip.

4. The semiconductor device according to claim 1,

wherein the entire via hole is formed by irradiating the insulating layer with laser light.

5. The semiconductor device according to claim 1,

wherein the externally connected pad includes a layer primarily containing Al.

6. The semiconductor device according to claim 1,

wherein the externally connected pad includes a layer primarily containing Cu.

7. The semiconductor device according to to claim 1,

wherein the externally connected pad is a wire bonding pad.

8. The semiconductor device according to claim 1,

wherein a thickness of the externally connected pad is at least 1.0 μ

m.

9. The semiconductor device according to claim 1,

wherein 95% decomposition temperature of the nonphotosensitive resin is lower than melting point of material forming the externally connected pad.

2. A semiconductor device, comprising:

a individually divided LSI chip including an externally connected pad;

an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in a position corresponding to the externally connected pad; and

a wiring layer extending along the insulating layer through the via hole to the externally connected pad,

wherein at least part of the via hole is formed by irradiating the insulating layer with laser light, and

the entire externally connected pad is located on a LSI chip side under a reference surface of the LSI chip.

19. The semiconductor device according to claim 2,

wherein the entire via hole is formed by irradiating the insulating layer with laser light.

21. The semiconductor device according to claim 2,

wherein the externally connected pad includes a layer primarily containing Al.

23. The semiconductor device according to claim 2,

wherein the externally connected pad includes a layer primarily containing Cu.

25. The semiconductor device according to claim 2,

wherein the externally connected pad is a wire bonding pad.

27. The semiconductor device according to claim 2,

wherein a thickness of the externally connected pad is at least 1.0 μ

m.

29. The semiconductor device according to claim 2, wherein 95% decomposition temperature of the nonphotosensitive resin is lower than melting point of material forming the externally connected pad.

3. A semiconductor device, comprising:

a individually divided LSI chip including an externally connected pad;

an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in a position corresponding to the externally connected pad; and

a wiring layer extending along the insulating layer through the via hole to the externally connected pad,

wherein at least part of the via hole is formed by irradiating the insulating layer with laser light, and

part of the externally connected pad is located on a LSI chip side under a reference surface of the LSI chip.

20. The semiconductor device according to claim 3,

wherein the entire via hole is formed by irradiating the insulating layer with laser light.

22. The semiconductor device according to claim 3,

wherein the externally connected pad includes a layer primarily containing Al.

24. The semiconductor device according to claim 3,

wherein the externally connected pad includes a layer primarily containing Cu.

26. The semiconductor device according to claim 3,

wherein the externally connected pad is a wire bonding pad.

28. The semiconductor device according to claim 3,

wherein a thickness of the externally connected pad is at least 1.0 μ

m.

30. The semiconductor device according to claim 3,

wherein 95% decomposition temperature of the nonphotosensitive resin is lower than melting point of material forming the externally connected pad.

10. (canceled)

11. A method for manufacturing a semiconductor device, comprising:

(1) preparing a individually divided LSI chip including an externally connected pad;

(2) forming an insulating layer made of a nonphotosensitive resin on the LSI chip;

(3) irradiating a position on the insulating layer corresponding to the externally connected pad with laser light, to remove the insulating layer and then to form a via hole passing through the insulating layer so that the externally connected pad is exposed; and

(4) forming a wiring layer extending along the insulating layer through the via hole to the externally connected pad.

14. The method for manufacturing a semiconductor device according to claim 11,

wherein the externally connected pad includes a layer primarily containing Al.

15. The method for manufacturing a semiconductor device according to claim 11,

wherein the externally connected pad includes a layer primarily containing Cu.

16. The method for manufacturing a semiconductor device according to claim 11,

wherein the externally connected pad includes the same surface as a reference surface of the LSI chip.

17. The method for manufacturing a semiconductor device according to claim 11,

wherein the entire externally connected pad is located on a LSI chip side under a reference surface of the LSI chip.

18. The method for manufacturing a semiconductor device according to claim 11,

wherein part of the externally connected pad is located on a LSI chip side under a reference surface of the LSI chip.

12. A method for manufacturing a semiconductor device, comprising:

(A) preparing a individually divided LSI chip including an externally connected pad;

(B) forming an insulating layer made of a nonphotosensitive resin on the LSI chip;

(C) irradiating a position on the insulating layer corresponding to the externally connected pad with laser light, to form an opening in the insulating layer in such a way that part of the insulating layer is left in the position corresponding to the externally connected pad;

(D) carrying out dry etching or wet etching at bottom of the opening, to remove the insulating layer left in the position corresponding to the externally connected pad, and then to form a via hole passing through the insulating layer so that the externally connected pad is exposed

(E) forming a wiring layer extending along the insulating layer through the via hole to the externally connected pad.

13. The method for manufacturing a semiconductor device according to claim 12,

wherein the externally connected pad includes an Al layer primarily containing Al and a TiN layer provided as an overlying layer on the Al layer, and

in step (D), the dry etching is carried out to remove the insulating layer and the TiN layer and then to expose the Al layer of the externally connected pad.

31. The method for manufacturing a semiconductor device according to claim 12,

wherein the externally connected pad includes a layer primarily containing Al.

32. The method for manufacturing a semiconductor device according to claim 12,

wherein the externally connected pad includes a layer primarily containing Cu.

33. The method for manufacturing a semiconductor device according to claim 12,

wherein the externally connected pad includes the same surface as a reference surface of the LSI chip.

34. The method for manufacturing a semiconductor device according to claim 12,

wherein the entire externally connected pad is located on a LSI chip side under a reference surface of the LSI chip.

35. The method for manufacturing a semiconductor device according to claim 12,

wherein part of the externally connected pad is located on a LSI chip side under a reference surface of the LSI chip.