THREE-DIMENSIONAL INTEGRATED HETEROGENEOUS SEMICONDUCTOR STRUCTURE

• US 20090294984A1
• Filed: 05/28/2008
• Published: 12/03/2009
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: ZHU, HUILONG
• Granted Patent: US 7,741,645 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A first set of semiconductor devices is formed on a first semiconductor substrate comprising a first semiconductor material having a first melting point. A first via-level dielectric layer containing first contact vias is formed on the first semiconductor substrate. A second semiconductor substrate comprising a second semiconductor material having a second melting point lower than the first melting point is formed either by bonding or deposition. A second set of semiconductor devices is formed on the second semiconductor substrate. A second via-level dielectric layer, second contact vias contacting the second set of semiconductor devices, and inter-substrate vias electrically connecting the first contact vias are thereafter formed. A metal interconnect layer containing a metal interconnect structure is formed over the second via-level dielectric layer to electrically connect the first and second set of semiconductor devices through the second contact vias and the inter-substrate vias.

Claims

1. A semiconductor structure comprising:

a first semiconductor substrate comprising a first semiconductor material having a first melting point;

a first set of semiconductor devices abutting said first semiconductor substrate;

a via-level dielectric layer located on said first set of semiconductor devices and containing first contact vias contacting said first set of semiconductor devices;

a second semiconductor substrate located over said first semiconductor substrate and said first set of semiconductor devices and comprising a second semiconductor material having a second melting point, wherein said second melting point is lower than said first melting point; and

a second set of semiconductor devices abutting said second semiconductor substrate.

2. The semiconductor structure of claim 1, further comprising a planar dielectric layer vertically abutting a top surface of said via-level dielectric layer and a bottom surface of said second semiconductor substrate.

3. The semiconductor structure of claim 1, further comprising another via-level dielectric layer located on said second set of semiconductor devices and containing second contact vias contacting said second set of semiconductor devices and inter-substrate vias electrically connected to said first set of semiconductor devices.

4. The semiconductor structure of claim 3, further comprising a set of metal lines embedded in an interconnect level dielectric layer and vertically abutting said second contact vias and said inter-substrate vias.

5. The semiconductor structure of claim 4, further comprising another set of metal lines embedded in another interconnect level dielectric layer and vertically abutting bottom surfaces of said inter-substrate vias and top surfaces of said first contact vias.

6. The semiconductor structure of claim 5, wherein said inter-substrate vias are laterally aligned to said another set of metal lines.

7. The semiconductor structure of claim 4, wherein bottom surfaces of said inter-substrate vias vertically abut top surfaces of said first contact vias.

8. The semiconductor structure of claim 7, wherein said inter-substrate vias are laterally aligned to said first contact vias.

9. The semiconductor structure of claim 1, wherein said first semiconductor substrate is single crystalline and said second semiconductor substrate is single crystalline or polycrystalline.

10. The semiconductor structure of claim 1, further comprising:

first metal semiconductor alloy regions abutting said first semiconductor substrate and comprising an alloy of a first metal and said first semiconductor material and abutting said first contact vias; and

second metal semiconductor alloy regions abutting said second semiconductor substrate and comprising an alloy of a second metal and said second semiconductor material and abutting said second contact vias.

11. The semiconductor structure of claim 1, wherein said first semiconductor material is silicon and said second semiconductor material is a silicon germanium alloy or a compound semiconductor material.

12. A method of forming a semiconductor structure comprising:

forming a first set of semiconductor devices directly on a first semiconductor substrate comprising a first semiconductor material having a first melting point;

forming a via-level dielectric layer and first contact vias on said first set of semiconductor devices;

forming a second semiconductor substrate comprising a second semiconductor material having a second melting point over said via-level dielectric layer, wherein said second melting point is lower than said first melting point; and

forming a second set of semiconductor devices directly on said second semiconductor substrate.

13. The method of claim 12, further comprising:

forming another via-level dielectric layer and second contact vias on said second set of semiconductor devices; and

forming inter-substrate vias electrically connected to said first set of semiconductor devices through said other via-level dielectric layer and said via-level dielectric layer.

14. The method of claim 13, further comprising:

forming an interconnect level dielectric layer on said other via-level dielectric layer; and

forming a set of metal lines in said interconnect level dielectric layer and directly on said second contact vias and said inter-substrate vias.

15. The method of claim 14, further comprising:

forming another interconnect level dielectric layer on said via-level dielectric layer; and

forming another set of metal lines in said other interconnect level dielectric layer and directly on top surfaces of said first contact vias, wherein said inter-substrate vias are formed in lateral alignment with said another set of metal lines.

16. The method of claim 13, further comprising forming a planar dielectric layer on said via-level dielectric layer, wherein said second semiconductor substrate is formed directly on a top surface of said planar dielectric layer, and wherein said inter-substrate vias are formed through said planar dielectric layer.

17. The method of claim 16, wherein said planar dielectric layer is formed directly on a top surface of said via-level dielectric layer, wherein said second semiconductor substrate is formed directly on a top surface of said planar dielectric layer, and wherein said inter-substrate vias are formed through said planar dielectric layer and directly on top surfaces of said first contact vias in lateral alignment with said first contact vias.

18. The method of claim 13, further comprising:

forming first metal semiconductor alloy regions comprising an alloy of a first metal and said first semiconductor material directly on said first semiconductor substrate, wherein said first contact vias from formed directly on said first metal semiconductor alloy regions; and

forming second metal semiconductor alloy regions comprising an alloy of a second metal and said second semiconductor material directly on said second semiconductor substrate, wherein said second contact vias are formed directly on said second metal semiconductor alloy regions.

19. The method of claim 12, further comprising:

forming a planar dielectric layer on said via-level dielectric layer; and

bonding a bottom surface of said second semiconductor substrate directly on a top surface of said planar dielectric layer.

20. The method of claim 12, further comprising:

forming a planar dielectric layer on said via-level dielectric layer; and

forming said second semiconductor substrate directly on a top surface of said planar dielectric layer by deposition of said second semiconductor material.