Voltage Reference With Improved Linearity Addressing Variable Impedance Characteristics At Output Node

• US 20090295363A1
• Filed: 05/29/2008
• Published: 12/03/2009
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pentakota, Visvesvaraya Appala, Udupa, Anand Hariraj
• Granted Patent: US 8,248,055 B2
• Time in Patent Office: Days
• US Class Current: 323/369
• CPC Class Codes: H03F 2203/45136 One differential amplifier in IC-block form being shown
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45534 the FBC comprising multiple switches and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.

Claims

1. An article of manufacture containing a voltage reference providing an output voltage on an output node, said voltage reference for driving an external component offering a load at said output node, said article of manufacture comprising:

a voltage generator to generate a voltage signal at a first node;

a first signal path between said first node and said output node, wherein said voltage signal is provided via said first signal path to said output node, said first signal path being characterized by a first resistance;

a second signal path coupled between said output node and a reference terminal, wherein said second signal path is characterized by a second resistance; and

a programmable resistance in series with said first resistance in said first signal path,

whereby non-linearity of said output voltage can be reduced by varying a magnitude of said programmable resistance.

2. The article of manufacture of claim 1, wherein said first signal path comprises:

a buffer coupled to receive said voltage signal from said first node, wherein said programmable resistance is coupled between an output of said buffer and said output node.

3. The article of manufacture of claim 2, wherein said programmable resistance is hard programmed to a value such that the output resistance of said buffer at least substantially equals said second resistance.

4. The article of manufacture of claim 3, wherein said programmable resistance comprises:

a plurality of resistors connected in series between said output of said buffer and said output node, a sequence of junctions being formed between each pair of resistors, said output of said buffer and a first one of said plurality of resistors, and said output node and a last one of said plurality of resistors; and

a plurality of switches, each of said plurality of switches to connect a corresponding one of said sequence of junctions and a common node.

5. The article of manufacture of claim 4, wherein said buffer contains an inverting terminal and a non-inverting terminal, said voltage reference further comprising:

a first resistor coupled between said inverting terminal and said first node; and

a second resistor coupled between said inverting terminal and said common node,

wherein said non-inverting terminal is connected to a reference potential.

6. The article of manufacture of claim 4, wherein said buffer contains an inverting terminal and a non-inverting terminal, wherein said first node is connected to said non-inverting terminal and said inverting terminal is connected to said common node.

7. The article of manufacture of claim 2, further comprises an analog to digital converter (ADC) to receive said output voltage as a reference signal and to convert an input sample to a corresponding digital code representing a strength of voltage of said input sample in relation to said output voltage.

8. The article of manufacture of claim 7, wherein said ADC comprises a plurality of stages, each stage containing an amplifier, a plurality of capacitors and a plurality of switches, said plurality of switches being operable to connect a number of capacitors to said output voltage depending on a strength of said input sample.

9. The article of manufacture of claim 7, further comprises a frequency detector block to measure a frequency of a sampling clock used in sampling an input signal containing said input sample, and to set said programmable resistance to a specific value according to said frequency such that the output resistance of said buffer at least substantially equals said second resistance at said frequency.

10. The article of manufacture of claim 9, further comprising a memory storing a look-up table to store a plurality of entries, with each entry specifying a value of said programmable resistance for a corresponding value of said frequency, wherein said frequency detector block is operable to examine said look-up table and determine said specific value according to the measured value of said frequency.

11. A device comprising:

a processor to process a sequence of digital values;

an analog to digital converter (ADC) to generate said sequence of digital values from an input signal based on a reference voltage; and

a voltage reference to generate an output voltage as said reference voltage on an output node, said voltage reference comprising;

a voltage generator to generate a voltage signal at a first node;

a first signal path between said first node and said output node, wherein said voltage signal is provided via said first signal path to said output node, said first signal path being characterized by a first resistance;

a second signal path coupled between said output node and a reference terminal, wherein said second signal path is characterized by a second resistance; and

a programmable resistance in series with said first resistance in said first signal path,

whereby non-linearity of said output voltage can be reduced by varying a magnitude of said programmable resistance.

12. The device of claim 11, wherein said first signal path comprises:

a buffer coupled to receive said voltage signal from said first node, wherein said programmable resistance is coupled between an output of said buffer and said output node.

13. The device of claim 12, wherein said programmable resistance is hard programmed to a value such that the output resistance of said buffer at least substantially equals said second resistance.

14. The device of claim 13, wherein said programmable resistance comprises:

a plurality of resistors connected in series between said output of said buffer and said output node, a sequence of junctions being formed between each pair of resistors, said output of said buffer and a first one of said plurality of resistors, and said output node and a last one of said plurality of resistors; and

a plurality of switches, each of said plurality of switches to connect a corresponding one of said sequence of junctions and a common node.

15. The device of claim 14, wherein said buffer contains an inverting terminal and a non-inverting terminal, said voltage reference further comprising:

a first resistor coupled between said inverting terminal and said first node; and

a second resistor coupled between said inverting terminal and said common node, wherein said non-inverting terminal is connected to a reference potential.

16. The device of claim 12, further comprises an analog to digital converter (ADC) to receive said output voltage as a reference signal and to convert an input sample to a corresponding digital code representing a strength of voltage of said input sample in relation to said output voltage.

17. The device of claim 16, wherein said ADC comprises a plurality of stages, each stage containing an amplifier, a plurality of capacitors and a plurality of switches, said plurality of switches being operable to connect a number of capacitors to said output voltage depending on a strength of said input sample.

18. The device of claim 16, further comprises a frequency detector block to measure a frequency of a sampling clock used in sampling an input signal containing said input sample, and to set said programmable resistance to a specific value according to said frequency such that the output resistance of said buffer at least substantially equals said second resistance at said frequency.

19. The device of claim 18, further comprising a memory storing a look-up table to store a plurality of entries, with each entry specifying a value of said programmable resistance for a corresponding value of said frequency,

wherein said frequency detector block is operable to examine said look-up table and determine said specific value according to the measured value of said frequency.

20. The device of claim 17, further comprising an analog processor to receive an analog signal at a first frequency and generating said input signal at a lower frequency than said first frequency, wherein said input signal at said lower frequency is processed by said ADC.

21. A method of providing voltage references with reduced non-linearity, said method comprising:

selecting a component having portions driven by a voltage reference, said voltage reference designed to contain a programmable output resistance portion, wherein said programmable output resistance portion is designed to be configurable in a plurality of magnitudes, wherein said component is designed to receive an input and generate a corresponding output when driven by said voltage reference;

setting said programmable output resistance portion to a sequence of magnitudes;

providing a sequence of inputs to said component, wherein each of said sequence of inputs is provided corresponding to a corresponding one of said sequence of magnitudes such that each of a sequence of outputs is generated by said component in response to a corresponding one of a magnitude-sequence combination;

examining said sequence of outputs to determine an optimum magnitude at which said component provides a desired set of outputs in response to corresponding inputs; and

hard-programming said programmable output resistance portion to said optimum magnitude.

22. The method of claim 21, wherein said component is an analog to digital converter (ADC), said sequence of inputs is a sine-wave, and said desired set of outputs contains a third harmonic of said sine-wave below a desired threshold.