TESTING OF MULTIPLE INTEGRATED CIRCUITS

• US 20090295415A1
• Filed: 05/30/2008
• Published: 12/03/2009
• Est. Priority Date: 05/30/2008
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pelley, Perry H. III, Pessoa, Lucio F. C.
• Granted Patent: US 8,294,483 B2
• Time in Patent Office: Days
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

Claims

1. A method for testing one or more integrated circuits, the method comprising:

simultaneously receiving via carrierless UWB radio frequency signaling an input test value from one antenna of a test probe at a first input of a first integrated circuit and at a second input of a second integrated circuit;

providing, from a first output of the first integrated circuit, a first output test value generated in response to the input test value; and

providing, from a second output of the second integrated circuit, a second output test value generated in response to the input test value.

2. The method of claim 1, wherein the providing, from the first output of the first integrated circuit, the first output test value generated in response to the input test value further comprises:

transmitting the first output test value via carrierless UWB radio frequency signaling.

3. The method of claim 2, wherein the providing, from the second output of the second integrated circuit, the second output test value generated in response to the input test value further comprises:

transmitting the second output test value via carrierless UWB radio frequency signaling.

4. The method of claim 3, wherein the first output test value and the second output test value are transmitted via carrierless UWB radio frequency signaling at least partially concurrently with each other.

5. The method of claim 1, wherein the providing, from the first output of the first integrated circuit, the first output test value generated in response to the input test value comprises:

transmitting, via wired signaling, the first output test value from the first integrated circuit to a tester station, the test probe coupled to the tester station.

6. The method of claim 5, wherein the first output of the first integrated circuit and the second output of the second integrated circuit are configured as a scan chain to output to the first output test value and the second output test value.

7. The method of claim 1, further comprising:

bringing the one antenna within a predetermined distance of the first and second integrated circuits, but not in physical contact with either of the first or second integrated circuits.

8. The method of claim 1, wherein the simultaneously receiving comprises:

simultaneously receiving via carrierless UWB radio frequency signaling the input test value from a plurality of antennas of the test probe to the first input of the first integrated circuit and to the second input of the second integrated circuit.

9. The method of claim 1, wherein the providing, from the second output of the second integrated circuit, the second output test value generated in response to the input test value comprises:

transmitting, via optical signaling, the second output test value from the second integrated circuit to a tester station, the test probe coupled to the tester station.

10. The method of claim 1, further comprising:

providing a semiconductor wafer, the semiconductor wafer comprising a first die having the first integrated circuit and a second die, spaced apart from the first die, and having the second integrated circuit.

11. A method for testing a plurality of die in a wafer, the method comprising:

providing a semiconductor wafer having a first die and a second die;

simultaneously receiving via carrierless UWB radio frequency signaling an input test value from one antenna of a test probe at a first input of the first die and at a second input of the second die;

providing, from a first output of the first die, a first output test value generated in response to the input test value;

providing, from a second output of the second die, a second output test value generated in response to the input test value; and

after the providing the first output test value and the providing the second output test value, singulating the wafer.

12. The method of claim 11, wherein the providing, from the first output of the first die, the first output test value generated in response to the input test value further comprises:

transmitting the first output test value via carrierless UWB radio frequency signaling.

13. The method of claim 12, wherein the providing, from the second output of the second die, the second output test value generated in response to the input test value further comprises:

transmitting the second output test value via carrierless UWB radio frequency signaling.

14. The method of claim 13, wherein the first output test value and the second output test value are transmitted via carrierless UWB radio frequency signaling at least partially concurrently with each other.

15. The method of claim 11, wherein the providing, from the first output of the first die, the first output test value generated in response to the input test value comprises:

transmitting, via a wire, the first output test value from the first die to a tester station, the test probe coupled to the tester station.

16. The method of claim 15, wherein the first output of the first die and the second output of the second die are configured as a scan chain to output to the first output test value and the second output test value.

17. A tester, comprising:

a tester probe comprising a first antenna, the first antenna simultaneously provides, via carrierless UWB radio frequency signaling, a first input test value to a first input of a first integrated circuit and a second input of a second integrated circuit; and

a test station, coupled to the tester probe, the test station receives, from the first integrated circuit, a first output test value generated in response to the first input test value and receives, from the second integrated circuit, a second output test value generated in response to the first input test value.

18. The tester of claim 17, wherein the tester probe further comprises a carrierless UWB radio frequency receiver which receives the first output test value and the second output test value.

19. The tester of claim 17, wherein the first integrated circuit and the second integrated circuit are located on a same semiconductor wafer when the first antenna simultaneously provides the input test value and when the test station receives the first and second output test values.

20. The tester of claim 17, wherein the tester probe comprises a plurality of antennas, wherein each of the plurality of antennas simultaneously provides a second input test value to at least two integrated circuit test inputs.