Systems and Methods of Digital Isolation with AC/DC Channel Merging

• US 20090295451A1
• Filed: 05/29/2008
• Published: 12/03/2009
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Larkin, David Leonard, Jordanger, Ricky Dale, Stout, David Wayne
• Granted Patent: US 7,755,400 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation

Abstract

Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

Claims

1. A method comprising:

receiving an input;

combining the input with a delay in a combiner;

triggering the output of the combiner;

buffering the output of the combiner to produce a buffered output;

inverting the output of the combiner to produce an inverted output;

applying the buffered output to a first isolator to produce a first isolated signal;

applying the inverted output to a second isolator to produce a second isolated signal;

comparing the first isolated signal and the second isolated signal using a window comparator;

applying an output of the window comparator to an R-S flip-flop latch;

filtering an output of the R-S flip-flop latch;

buffering an output of the filtering; and

transmitting an output of the buffering.

2. The method of claim 1, wherein at least one of the first and second isolators comprises at least one of a capacitive isolator and an inductive isolator.

3. The method of claim 1, wherein the window comparator comprises a first comparator and a second comparator fabricated on one semiconductor die.

4. The method of claim 3, wherein the comparators have substantially equal offset voltages.

5. An apparatus comprising:

an input buffer for buffering an input signal;

gating logic coupled to the input buffer, the gating logic for gating an output of the input buffer;

a delay element coupled to the gating logic, the delay element for introducing delay into the gating logic;

a trigger coupled to the gating logic, the trigger for triggering the gating logic;

a buffer/inverter coupled to the gating logic, the buffer inverter for buffering an output of the gating logic to produce a buffered output and for inverting the output of the gating logic to produce an inverted output;

an isolation stage coupled to the buffer/inverter, the isolation stage for isolating an output of the buffer to produce an isolated buffered output and an output of the inverter to produce an isolated inverted output;

a comparator stage coupled to the isolation stage, the comparator stage for comparing the isolated buffer output of the isolation stage with the isolated inverted output of the isolation stage;

an R-S latch coupled to the comparator stage, the R-S latch for latching an output of the comparator stage; and

a filter coupled to the R-S latch, the filter for filtering an output of the R-S latch to provide an output signal associated with the state of the input signal.

6. The apparatus of claim 5, wherein the isolation stage comprises at least one of a capacitive isolator and an inductive isolator.

7. The apparatus of claim 5, wherein the delay element comprises an RC circuit.

8. The apparatus of claim 5, wherein the trigger comprises a one-shot timer.

9. The apparatus of claim 5, wherein the comparator stage comprises a window comparator.

10. The apparatus of claim 9, wherein the window comparator comprises a first comparator and a second comparator, the first and second comparators fabricated on one semiconductor die.

11. A method comprising:

receiving an input signal with a first state;

combining an update pulse with a second state and the input signal to produce an updated signal;

transmitting the updated signal across an isolation barrier; and

setting a third state of an output signal state based on the first state and the second state.

12. The method of claim 11, wherein adding the update pulse comprises:

combining the input pulse with a delay in a combiner; and

triggering the output of the combiner.

13. The method of claim 12, wherein the delay is provided by a timer.

14. The method of claim 12, wherein the triggering is performed by a one-shot timer.

15. The method of claim 11, wherein the isolation barrier comprises a passive isolation barrier.

16. The method of claim 15, wherein the passive isolation barrier comprises at least one of a capacitor and an inductor.

17. The method of claim 11, wherein setting the output signal state comprises setting the output of a latch.

18. The method of claim 17, wherein the latch is set based on the output of a comparison stage.

19. The method of claim 11, wherein setting the output signal state comprises filtering the update pulse from the updated signal.

20. The method of claim 11, further comprising setting the output of the isolation barrier with a DC reference voltage.