Systems and Methods of Digital Isolation with AC/DC Channel Merging
First Claim
1. A method comprising:
- receiving an input;
combining the input with a delay in a combiner;
triggering the output of the combiner;
buffering the output of the combiner to produce a buffered output;
inverting the output of the combiner to produce an inverted output;
applying the buffered output to a first isolator to produce a first isolated signal;
applying the inverted output to a second isolator to produce a second isolated signal;
comparing the first isolated signal and the second isolated signal using a window comparator;
applying an output of the window comparator to an R-S flip-flop latch;
filtering an output of the R-S flip-flop latch;
buffering an output of the filtering; and
transmitting an output of the buffering.
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Abstract
Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.
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Citations
20 Claims
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1. A method comprising:
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receiving an input; combining the input with a delay in a combiner; triggering the output of the combiner; buffering the output of the combiner to produce a buffered output; inverting the output of the combiner to produce an inverted output; applying the buffered output to a first isolator to produce a first isolated signal; applying the inverted output to a second isolator to produce a second isolated signal; comparing the first isolated signal and the second isolated signal using a window comparator; applying an output of the window comparator to an R-S flip-flop latch; filtering an output of the R-S flip-flop latch; buffering an output of the filtering; and transmitting an output of the buffering. - View Dependent Claims (2, 3, 4)
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5. An apparatus comprising:
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an input buffer for buffering an input signal; gating logic coupled to the input buffer, the gating logic for gating an output of the input buffer; a delay element coupled to the gating logic, the delay element for introducing delay into the gating logic; a trigger coupled to the gating logic, the trigger for triggering the gating logic; a buffer/inverter coupled to the gating logic, the buffer inverter for buffering an output of the gating logic to produce a buffered output and for inverting the output of the gating logic to produce an inverted output; an isolation stage coupled to the buffer/inverter, the isolation stage for isolating an output of the buffer to produce an isolated buffered output and an output of the inverter to produce an isolated inverted output; a comparator stage coupled to the isolation stage, the comparator stage for comparing the isolated buffer output of the isolation stage with the isolated inverted output of the isolation stage; an R-S latch coupled to the comparator stage, the R-S latch for latching an output of the comparator stage; and a filter coupled to the R-S latch, the filter for filtering an output of the R-S latch to provide an output signal associated with the state of the input signal. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method comprising:
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receiving an input signal with a first state; combining an update pulse with a second state and the input signal to produce an updated signal; transmitting the updated signal across an isolation barrier; and setting a third state of an output signal state based on the first state and the second state. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification