SYSTEM AND METHOD FOR REDUCING POWER DISSIPATION IN AN ANALOG TO DIGITAL CONVERTER

• US 20090295609A1
• Filed: 06/09/2007
• Published: 12/03/2009
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: Cosmic Circuits Private Limited
• Original Assignee: Cosmic Circuits Private Limited
• Inventors: Bhowmik, Prasenjit, Krishnan, Sundararajan, Khatri, Mukesh, Chakkirala, Sumanth, Ghosh, Sanjeeb Kumar, Srinivasan, C., Venkatesh, T. S., Bhattacharya, Prasun Kali, Chandrashekar, L., Easwaran, Prakash
• Granted Patent: US 7,821,436 B2
• Time in Patent Office: Days
• US Class Current: 341/122
• CPC Class Codes: H03M 1/0641 the dither being a random signal
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Claims

1. An analog to digital converter (ADC) comprising:

a plurality of clock phases, each clock phase comprising an amplifying phase and a sample-and-hold phase for amplifying and sampling an input analog input signal, said ADC comprising;

(i) a residue amplifier;

(ii) each of said plurality of amplifying phases comprising;

a feedback capacitor;

a first set of switches operable to couple the residue amplifier for amplifying a residue output of an immediately preceding clock phase, wherein said residue amplifier generates an amplified residue output;

a second set of switches operable to couple said feedback capacitor to said residue amplifier for storing said amplified residue output;

(iii) each of said plurality of sample-and-hold phases comprising;

said second set of switches operable to couple said feedback capacitor of said amplifying phase to said residue amplifier; and

a third set of switches operable to couple a next stage sampling capacitor to said residue amplifier for sampling said amplified residue output of the residue amplifier stored on said feedback capacitor.

2. The analog to digital converter of claim 1, wherein said first set of switches of said amplifying phase comprise:

a first switch and a second switch coupling a sampling capacitor to the residue amplifier.

3. The analog to digital converter of claim 1, wherein said second set of switches in the sample-and-hold phase comprises:

a third switch and a fourth switch for coupling said feedback capacitor to the residue amplifier in feedback and for decoupling said feedback capacitor from the residue amplifier in said amplifying phase.

4. The analog to digital converter of claim 1, wherein said third set of switches in the sample-and-hold phase comprises:

a fifth switch and a sixth switch being for coupling the next stage sampling capacitor to the residue amplifier and for decoupling the next stage sampling capacitor from the residue amplifier in said amplifying phase.

5. The analog to digital converter of claim 1, wherein a power dissipated in the ADC is reduced by sharing a load on the residue amplifier between said sample-and-hold phase and said amplifying phase.

6. The analog to digital converter of claim 5, wherein the load on the residue amplifier is shared between said sample-and-hold phase and said amplifying phase by avoiding a slowing-effect of the low feedback factor while the next stage capacitance is sampling in the sample-and-hold phase and a loading effect of the next stage sampling capacitor is avoided while amplifying the residue value in the amplifying phase.

7. The analog to digital converter of claim 1, wherein the analog to digital converter is a pipelined analog to digital converter.

8. A method for reducing power dissipated in an analog to digital converter (ADC) comprised of a plurality of clock phases, each clock phase comprising an amplifying phase and a sample-and-hold phase for respectively amplifying and sampling an analog input signal, comprising the steps of:

(a) receiving, in a current amplifying phase, a residue value output from a residue amplifier in a previous clock phase; and

(b) amplifying said residue value during said current amplifying phase, thereby eliminating a load effect on said residue amplifier;

(c) driving a large load on the residue amplifier and increasing a feedback factor in the sample-and-hold phase and eliminating the sampling capacitance of a previous stage during a sample-and-hold phase, thereby eliminating a low feedback factor; and

(d) outputting the residue value from the residue amplifier at the termination of a sample-and-hold phase, the residue value being derived from said sampled analog input signal;

9. The method of claim 8, wherein power dissipated in said analog to digital converter (ADC) is reduced by sharing the large load on the residue amplifier between both said sample-and-hold phase and said amplifying phase.

10. A method for reducing power dissipated in an analog to digital converter (ADC), the method comprising the step of:

holding a residue value of a phase for two consecutive phases for each of a plurality of clock phases, whereby value input to a comparator is available for two consecutive phases, wherein said holding step further comprises;

calculating said residue value in said amplifying phase using a first set of comparators, said amplifying phase for amplifying an output of a previous sample-and-hold phase; and

selecting a threshold value of a second set of comparators in a subsequent sample-and-hold phase based on the residue value calculated at said calculating step.

11. The method of claim 10, wherein the number of comparators used in said analog to digital converter is reduced by sharing the residue value between two consecutive phases from among the plurality of clock phases whereby power dissipated is reduced.

12. The method of claim 10, wherein the holding step further comprises:

reducing the speed requirement on the comparator whereby reducing power dissipated.

13. The method of claim 10, wherein the sample-and-hold phase and the amplifying phase in each of said plurality of clock phases occur in a sequentially continuous manner.