Memory device and memory programming method

• US 20090296466A1
• Filed: 04/16/2009
• Published: 12/03/2009
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Kyoung Lae, Kim, Yong June, Kim, Jae Hong, Chae, Dong Hyuk
• Granted Patent: US 7,924,624 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

Claims

1. A memory device comprising:

a multi-bit cell array that includes a plurality of memory cells;

a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group based on the extracted state information, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and

a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

2. The memory device of claim 1, wherein the controller assigns the first verify voltage to the plurality of memory cells in a first time interval, and in a second time interval after the first time interval is completed, sets, as the first group, a memory cell with the threshold voltage greater than or equal to the first verify voltage and sets, as the second group, remaining memory cells excluding the first group from the plurality of memory cells.

3. The memory device of claim 2, wherein the programming unit applies, a reference number of times, a pulse corresponding to a program voltage to the plurality of memory cells in the first time interval.

4. The memory device of claim 2, wherein, when a number of memory cells with the threshold voltage greater than or equal to the first verify voltage among the plurality of memory cells is greater than a reference number, the controller terminates the first time interval.

5. The memory device of claim 2, wherein the controller sets, as the second verify voltage, a voltage greater than the first verify voltage.

6. The memory device of claim 1, wherein the programming unit applies a pulse corresponding to a program voltage to a gate terminal of each of the memory cells, and applies a program condition voltage to each of bit lines that are connected to a memory cell with a threshold voltage less than the first verify voltage, among the memory cells of the first group, and that are connected to a memory cell with a threshold voltage less than the second verify voltage, among the memory cells of the second group.

7. The memory device of claim 6, wherein the programming unit applies a pulse corresponding to a first program voltage and then applies a pulse corresponding to a second program voltage greater than the first program voltage.

8. The memory device of claim 1, wherein the controller assigns the first verify voltage to the memory cells of the first group and assigns the second verify voltage to the memory cells of the second group, based on data to be programmed in the plurality of memory cells.

9. A memory programming method comprising:

setting a verify voltage of a plurality of memory cells as a first voltage level;

applying a first program voltage to a gate terminal of each of the plurality of memory cells to increase a threshold voltage of each of the memory cells;

dividing the plurality of memory cells into first memory cells and remaining memory cells, the first memory cells being memory cells, from among the plurality of memory cells, with threshold voltages greater than or equal to the verify voltage of the first voltage level;

resetting the verify voltage of remaining memory cells, excluding the first memory cells, as a second voltage level greater than the first voltage level; and

applying a second program voltage to the gate terminal of each of the memory cells.

10. The method of claim 9, wherein

the verify voltage of the remaining memory cells is reset when a number of the first memory cells is greater than or equal to a reference number after the first program voltage is applied.

11. The method of claim 10, further comprising:

identifying, from the plurality of memory cells, a memory cell with a threshold voltage less than the set verify voltage or the reset verify voltage;

applying a program condition voltage to a bit line connected to the identified memory cell while the second program voltage is being applied; and

applying a program inhibit voltage to a bit line connected to the remaining memory cells excluding the identified memory cell while the second program voltage is being applied.

12. The method of claim 10, further comprising:

setting, as the second program voltage, a voltage level greater than the first program voltage.

13. The method of claim 10, wherein the resetting includes:

identifying the first memory cell; and

maintaining a verify voltage of the first memory cell at the first voltage level.

14. The method of claim 10, wherein the resetting includes maintaining the verify voltage of the plurality of memory cells at the first voltage level when the number of first memory cells is less than the reference number.

15. The method of claim 9, wherein

the first program voltage is applied a reference number of times, and

the verify voltage of the remaining memory cells is reset after the first program voltage is applied the reference number of times.

16. The method of claim 15, further comprising:

identifying, from the plurality of memory cells, a memory cell with a threshold voltage less than the set verify voltage or the reset verify voltage;

applying a program condition voltage to a bit line connected to the identified memory cell while the second program voltage is being applied; and

applying a program inhibit voltage to a bit line connected to the remaining memory cells excluding the identified memory cell while the second program voltage is being applied.

17. The method of claim 15, further comprising:

setting, as the second program voltage, a voltage level greater than the first program voltage.

18. The method of claim 15, wherein the resetting includes:

identifying the first memory cell; and

maintaining a verify voltage of the first memory cell at the first voltage level.

19. The method of claim 15, wherein the applying of the first program voltage comprises:

identifying, from the plurality of memory cells, a memory cell with a threshold voltage less than the set verify voltage every time after the first program voltage is applied;

applying a program condition voltage to a bit line connected to the identified memory cell while the first program voltage is being applied; and

applying a program inhibit voltage to a bit line connected to remaining memory cells excluding the identified memory cell while the first program voltage is being applied.

20. A computer-readable recording medium storing a program for implementing the method of claim 10.

21. A computer-readable recording medium storing a program for implementing the method of claim 15.