Memory device and memory programming method

• US 20090296486A1
• Filed: 03/13/2009
• Published: 12/03/2009
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Kyoung Lae, Kim, Yong June, Kim, Jae Hong, Chae, Dong Hyuk
• Granted Patent: US 8,059,467 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

Claims

1. A memory device comprising:

a memory cell array including a plurality of memory cells;

a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and

a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse when the plurality of memory cells have reached a balanced state.

2. The memory device of claim 1, further comprising:

an identification unit configured to identify the memory cell having a threshold voltage lower than the verification voltage from among the plurality of memory cells each time after each of the plurality of pulses is applied.

3. The memory device of claim 1, wherein the programming unit applies the pulse a reference number of times during the first time interval.

4. The memory device of claim 1, wherein the control unit sets a first decision voltage lower than the verification voltage during the first time interval, and determines whether the first time interval is terminated based on a number of memory cells having a threshold voltage higher than or equal to the first decision voltage each time after each of the plurality of pulses is applied.

5. The memory device of claim 4, wherein the control unit increases the first decision voltage by the first increment each time after each of the plurality of pulses is applied, and terminates the first time interval when the number of memory cells having a threshold voltage higher than or equal to the first decision voltage is equal to a previously-counted number of memory cells having a threshold voltage higher than or equal to the first decision voltage.

6. The memory device of claim 1, wherein the control unit sets a first decision voltage lower than the verification voltage and a second decision voltage lower than the first decision voltage during the first time interval, and determines whether the first time interval is terminated based on a number of memory cells having a threshold voltage higher than or equal to the first decision voltage and a number of memory cells having a threshold voltage higher than or equal to the second decision voltage each time after each of the plurality of pulses is applied.

7. The memory device of claim 6, wherein, when an increment of a number of first memory cells having a threshold voltage higher than or equal to the second decision voltage and is lower than the first decision voltage is equal to an increment of a number of second memory cells having a threshold voltage higher than or equal to the first decision voltage, the control unit terminates the first time interval.

8. The memory device of claim 1, wherein the programming unit applies the plurality of pulses to increase a threshold voltage of the memory cell having a threshold voltage lower than the verification voltage from among the plurality of memory cells.

9. The memory device of claim 1, wherein the control unit sets the second increment to be greater than the first increment.

10. The memory device of claim 1, wherein the control unit sets the verification voltage with respect to each of the plurality of memory cells based on data to be programmed in the plurality of memory cells.

11. The memory device of claim 10, wherein the programming unit determines whether each of the plurality of pulses is applied to each of the plurality of memory cells based on the verification voltage being set with respect to each of the plurality of memory cells.

12. The memory device of claim 10, wherein the programming unit selects the verification voltage with respect to each of the plurality of memory cells from among a plurality of verification voltage candidates.

13. The memory device of claim 12, wherein the programming unit compares each of the plurality of verification voltage candidates and a threshold voltage of each of the plurality of memory cells each time after each of the plurality of pulses is applied.

14. The memory device of claim 1, wherein the control unit estimates a number of applications of the plurality of pulses, and determines an initial value of the program voltage based on the estimated number.

15. A memory programming method, the method comprising:

applying a pulse corresponding to a program voltage to a gate terminal of each of a plurality of memory cells;

applying a program condition voltage, while the pulse is applied, to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells;

determining an increment of the program voltage after the pulse is applied based on whether or not the plurality of memory cells have reached a balanced state;

increasing the program voltage by the determined increment; and

applying the pulse corresponding to the increased program voltage to a gate terminal of each of the plurality of memory cells.

16. The method of claim 15, wherein the determining includes:

determining a first increment as the increment of the program voltage when a number of applications of the pulse is less than a threshold; and

determining a second increment as the increment of the program voltage when the number of applications of the pulse is greater than or equal to the threshold.

17. The method of claim 15, further comprising:

setting a first decision voltage lower than the verification voltage after the pulse is applied,

wherein the determining determines the increment based on a number of memory cells having a threshold voltage higher than or equal to the first decision voltage.

18. The method of claim 17, further comprising:

increasing the first decision voltage by the increment after the pulse corresponding to the increased program voltage is applied,

wherein the determining includes

determining the first increment as the increment of the program voltage when the number of memory cells having a threshold voltage higher than or equal to the first decision voltage is equal to a previously-counted number of memory cells having a threshold voltage higher than or equal to the first decision voltage; and

determining a second increment greater than the first increment as the increment of the program voltage when the number of memory cells having a threshold voltage higher than or equal to the first decision voltage is different from the previously-counted number of memory cells having a threshold voltage higher than or equal to the first decision voltage.

19. The method of claim 15, further comprising:

setting a first decision voltage lower than the verification voltage and a second decision voltage lower than the first decision voltage after the pulse is applied,

wherein the determining determines the increment based on a number of memory cells having a threshold voltage higher than or equal to the first decision voltage and a number of memory cells having a threshold voltage higher than or equal to the second decision voltage.

20. The method of claim 19, wherein the determining includes:

calculating an increment of a number of first memory cells having a threshold voltage which is higher than or equal to the second decision voltage and is lower than the first decision voltage;

calculating an increment of a number of second memory cells having a threshold voltage higher than or equal to the first decision voltage;

determining a first increment as the increment of the program voltage when the increment of the number of first memory cells is greater than the increment of the number of second memory cells; and

determining a second increment as the increment of the program voltage when the increment of the number of first memory cells is equal to the increment of the number of second memory cells, the second increment being greater than the first increment.

21. A computer-readable recording medium storing a program for implementing the method of claim 15.