Multi-Pair Gigabit Ethernet Transceiver

• US 20090296791A1
• Filed: 08/03/2009
• Published: 12/03/2009
• Est. Priority Date: 11/09/1998
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Arthur Abnous, David E. Kruse, Henry Samueli, John L. Creigh, Mehdi Hatamian, Oscar E. Agazzi
• Inventors: Kruse, David E., Hatamian, Mehdi, Creigh, John L., Agazzi, Oscar E., Samueli, Henry, Abnous, Arthur
• Granted Patent: US 7,801,241 B2
• Time in Patent Office: Days
• US Class Current: 375/220
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/235 combined with adaptive equaliser
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 : not time-recursive
• CPC Class Codes: H04L 2025/0349 : as a feedback filter
• CPC Class Codes: H04L 2025/03496 : as a prediction filter
• CPC Class Codes: H04L 2025/03503 : as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 : Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 : Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03197 : methods of calculation involving metrics
• CPC Class Codes: H04L 25/03203 : Trellis search techniques
• CPC Class Codes: H04L 25/03235 : with state-reduction using feedback filtering
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03987 : Equalisation for sparse channels
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Claims

1-16. -16. (canceled)

17. An integrated circuit communication device comprising:

an intersymbol interference (ISI) compensation filter having a substantially inverse impulse response to the impulse response of a pulse shaping filter of a remote transmitter.

49. The integrated circuit communication device according to claim 17, wherein the ISI compensation filter comprises:

an inverse partial response filter having an impulse response substantially an inverse of an impulse response of a pulse shaping filter of a remote transmitter, so as to substantially compensate an input digital signal for an ISI component introduced by the pulse shaping filter of the remote transmitter.

50. The integrated circuit communication device according to claim 49, wherein the inverse partial response filter is implemented with a characteristic feedback gain factor K.

51. The integrated circuit communication device according to claim 50, wherein the inverse partial response filter operates in accordance with a non-zero value of the characteristic feedback gain factor K during communication initialization and wherein the value of the feedback gain factor K is ramped down to zero after a pre-defined interval.

160. The integrated circuit device of claim 17, further comprising an adaptive gain stage operable to adjust a gain of a signal that has been processed by the ISI compensation filter.

161. The integrated circuit device of claim 17 wherein the ISI compensation filter is programmable.

162. The integrated circuit device of claim 17 wherein the ISI compensation filter is operable to compensate intersymbol interference introduced by a pulse-shaping filter of a remote transmitter during communication initialization.

163. The integrated circuit device of claim 51, further comprising a decision feedback equalizer, and wherein the characteristic feedback gain factor K is ramped to zero after convergence of the decision feedback equalizer.

18-48. -48. (canceled)

52-159. -159. (canceled)

164. A method of processing a communication signal received at an integrated circuit communication device, the method comprising:

compensating intersymbol interference (ISI) introduced by a pulse shaping filter of a remote transmitter using an inverse response filter having a substantially inverse impulse response to the impulse response of the pulse shaping filter of the remote transmitter.

165. The method of claim 164 wherein the inverse impulse response filter is implemented with a characteristic feedback gain factor K.

166. The method of claim 165 further comprising operating the inverse response filter in accordance with a non-zero value of the characteristic feedback gain factor K during communication initialization and further comprising ramping the value of the feedback gain factor K down to zero after a pre-defined interval.

167. The method of claim 166, wherein the integrated circuit communication device comprises a decision feedback equalizer, and wherein the value of the feedback gain factor K is ramped down to zero after convergence of the decision feedback equalizer.

168. The method of claim 164, further comprising adaptively adjusting a gain of a signal that has been processed by the inverse response filter.

169. The method of claim 164 wherein the inverse response filter is programmable.

170. The method of claim 164 wherein the operation of compensating ISI introduced by the pulse shaping filter of the remote transmitter is performed during communication initialization.