METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA

• US 20090297019A1
• Filed: 08/03/2009
• Published: 12/03/2009
• Est. Priority Date: 11/18/2005
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Chang, Ellis, Rose, Peter, Park, Allen, Zafar, Khurram, Kekare, Sagar
• Granted Patent: US 8,923,600 B2
• Time in Patent Office: Days
• US Class Current: 382/145
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/20076 Probabilistic image processing
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/0008 checking presence/absence

Abstract

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Claims

1. A computer-implemented method for determining a defect criticality index for a defect detected on a wafer, comprising:

determining a probability that the defect will alter one or more electrical attributes of a device being fabricated on the wafer based on one or more attributes of design data, for the device, proximate the position of the defect in design data space;

determining the defect criticality index for the defect based on the probability that the defect will alter the one or more electrical attributes; and

storing the defect criticality index in a storage medium.

2. The method of claim 1, wherein the defect comprises a random defect.

3. The method of claim 1, wherein the defect comprises a systematic defect.

4. The method of claim 1, wherein the one or more electrical attributes comprise functionality of the device.

5. The method of claim 1, wherein the one or more electrical attributes comprise one or more electrical parametrics of the device.

6. The method of claim 1, wherein the one or more attributes of the design data comprise redundancy, net list, or some combination thereof.

7. The method of claim 1, wherein the one or more attributes of the design data comprise dimensions of features in the design data, density of features in the design data, or some combination thereof.

8. The method of claim 1, wherein said determining the probability comprises determining the probability using a correlation between electrical test results for the design data and the one or more attributes of the design data.

9. The method of claim 1, wherein said determining the probability comprises determining the probability based on the one or more attributes of the design data in combination with a probability of the position of the defect within the design data space, a position of the defect reported by an inspection system used to detect the defect, coordinate inaccuracy of the inspection system, a size of the defect, defect size error of the inspection system, or some combination thereof.

10. The method of claim 9, wherein the defect comprises a random defect.

11. The method of claim 1, wherein said determining the probability comprises determining the probability based on the one or more attributes of the design data in combination with one or more attributes of the defect.

12. The method of claim 11, wherein the defect comprises a systematic defect.

13. The method of claim 1, wherein said determining the defect criticality index comprises determining the defect criticality index for the defect based on the probability in combination with a classification assigned to the defect.

14. The method of claim 1, wherein the one or more attributes of the design data comprise one or more attributes of the design data for more than one design layer for the device.

15. The method of claim 1, further comprising determining the design data proximate the position of the defect by determining a position of inspection data in the design data space.

16. The method of claim 1, further comprising determining the design data proximate the position of the defect by defect alignment.

17. The method of claim 1, further comprising determining the design data proximate the position of the defect based, at least in part, on a position of the defect reported by an inspection system used to detect the defect, coordinate inaccuracy of the inspection system, one or more attributes of the design data, defect size, defect size error of the inspection system, or some combination thereof.

18. The method of claim 1, further comprising modifying the defect criticality index based on sensitivity of yield of the design data to defects.

19. The method of claim 1, further comprising altering a process performed on the defect based on the defect criticality index determined for the defect.

20. The method of claim 1, further comprising altering a process used to detect the defect based on the defect criticality index determined for the defect.

21. The method of claim 1, further comprising generating a process for inspection of additional wafers on which the device will be fabricated based on the defect criticality index determined for the defect.

22. The method of claim 1, wherein the computer-implemented method is performed by an inspection system used to detect the defect.

23. The method of claim 1, wherein the computer-implemented method is performed by a system other than an inspection system used to detect the defect.

24. A computer-implemented method for determining a memory repair index for a memory bank formed on a wafer, comprising:

determining a number of redundant rows and a number of redundant columns required to repair the memory bank based on defects located in an array block area of the memory bank;

comparing the number of the redundant rows required to repair the memory bank to an amount of available redundant rows for the memory bank;

comparing the number of the redundant columns required to repair the memory bank to an amount of available redundant columns for the memory bank;

determining the memory repair index for the memory bank based on results of said comparing the number of the redundant rows and said comparing the number of the redundant columns, wherein the memory repair index indicates if the memory bank is repairable; and

storing the memory repair index in a storage medium.

25. The method of claim 24, further comprising determining which of the defects located in the array block area will cause bits in the memory bank to fail and determining positions of the bits that will fail based on locations of the defects that will cause the bits to fail, wherein determining the number of the redundant rows and the number of the redundant columns required to repair the memory bank is performed using the positions of the bits that will fail.

26. The method of claim 24, further comprising altering one or more parameters of an electrical test process based on the memory repair index using a feed forward control technique.

27. The method of claim 24, further comprising altering one or more parameters of an electrical test process based on the memory repair index using a feed forward control technique such that if the memory bank is not repairable, a die in which the memory bank is located is not tested during the electrical test process.

28. The method of claim 24, further comprising altering one or more parameters of a repair process based on one or more attributes of the defects located in the array block area of the memory bank, the memory repair index, or some combination thereof.

29. The method of claim 24, wherein the defects comprise defects detected at a gate layer of the memory bank.

30. The method of claim 24, wherein the defects comprise defects detected at a metal layer of the memory bank.

31. The method of claim 24, further comprising predicting bit failure modes of the defects based on locations of the defects in the memory bank.

32. The method of claim 24, further comprising determining a defect criticality index for one or more of the defects located in the array block area, wherein determining the number of the redundant rows and the number of the redundant columns required to repair the memory bank is performed using the defect criticality indexes for the one or more of the defects.

33. The method of claim 24, wherein said comparing the number of the redundant rows is performed separately for each bank of a memory die, and wherein said comparing the number of the redundant columns is performed separately for each bank of the memory die.

34. The method of claim 24, further comprising determining the amount of the available redundant rows and the amount of the available redundant columns based on defects located in the redundant rows and the redundant columns of the memory bank.

35. The method of claim 24, further comprising determining the memory repair index for more than one memory bank formed in a die and predicting a repair yield for the die based on the memory repair indexes for the more than one memory bank.

36. The method of claim 24, further comprising determining, based on the memory repair index, if the amount of the available redundant columns, the amount of the available redundant rows, or some combination thereof in the memory bank should be evaluated by a designer of the memory bank.

37. The method of claim 24, further comprising determining the memory repair index for each memory bank in one or more dies on the wafer and determining a memory repair yield for the one or more dies based on the memory repair indexes for each memory bank.

38. The method of claim 37, further comprising performing wafer disposition based on the one or more memory repair yields for the one or more dies on the wafer.

39. The method of claim 24, wherein said comparing the number of the redundant rows comprises determining a fraction of the redundant rows needed to repair the memory bank, wherein said comparing the number of the redundant columns comprises determining a fraction of the redundant columns needed to repair the memory bank, and wherein said determining the memory repair index for the memory bank comprises determining the memory repair index based on the fraction of the redundant rows and the fraction of the redundant columns.

40. The method of claim 39, further comprising determining the memory repair index for each memory bank in one or more dies on the wafer and determining a memory repair yield for the one or more dies based on the memory repair indexes for each memory bank.

41. The method of claim 39, further comprising determining the memory repair index for each memory bank in one or more dies on the wafer, determining a memory repair yield for the one or more dies based on the memory repair indexes for each memory bank, and determining a memory repair yield for the wafer based on the memory repair yields for each of the one or more dies.

42. The method of claim 24, wherein the memory repair index further indicates a probability that the memory bank will not be repairable, the method further comprising determining the memory repair index for each memory bank in one or more dies on the wafer and determining a memory repair index for the one or more dies based on the memory repair index for each of the memory banks in the one or more dies, and wherein the memory repair indexes for the one or more dies indicate a probability that the one or more dies will not be repairable.

43. The method of claim 42, further comprising determining a wafer based yield prediction based on thresholding of the memory repair indexes for the one or more dies on the wafer.

44. The method of claim 24, further comprising determining a number of non-repairable defects in the memory bank based on a number of defects located in a decoder area of the memory bank, a number of defects located in a sense amp area of the memory bank, or some combination thereof.

45. The method of claim 24, wherein said determining the number of the redundant rows and the number of the redundant columns comprises determining a defect criticality index for each of the defects located in the array block area of the memory bank, comparing the defect criticality indexes to a predetermined threshold, and determining the number of the redundant rows and the number of the redundant columns required to repair all of the defects having a defect criticality index above the predetermined threshold.

46. The method of claim 24, further comprising determining a memory repair index for failure of the memory bank due to the defects located in the array block area of the memory bank.

47. The method of claim 24, further comprising determining a memory repair index for failure of the memory bank due to defects located in the redundant rows and the redundant columns for the memory bank.

48. The method of claim 24, further comprising generating a stacked map of like memory bank designs illustrating spatial correlations between defects detected in the memory banks.

49. The method of claim 24, further comprising determining the memory repair index on a die basis.

50. The method of claim 24, further comprising determining an index indicating if a die on the wafer will fail due to the defects located in the array block area.

51. The method of claim 24, further comprising determining the memory repair index for memory banks in a die on the wafer and generating a stacked map of the die illustrating spatial correlations between two or more of the memory banks indicated by the memory repair indexes to not be repairable.

52. The method of claim 24, further comprising determining the memory repair index for memory banks in a die on the wafer and generating a stacked map of a reticle used to form the memory banks on the wafer illustrating spatial correlations between two or more of the memory banks indicated by the memory repair indexes to not be repairable.

53. The method of claim 24, further comprising identifying memory banks of a die impacted by defects detected in the die and ranking the memory banks based on the impact of the defects on the memory banks.

54. The method of claim 24, further comprising determining a percentage of memory banks formed on the wafer impacted by defects in non-repairable areas of the memory banks.

55. The method of claim 24, further comprising generating a stacked wafer map of probable failures in memory banks formed on the wafer illustrating spatial correlations between the probable failures.

56. The method of claim 24, further comprising determining the memory repair index for more than one die formed on the wafer and ranking the more than one die based on the memory repair indexes.

57. A computer-implemented method for assigning classifications to defects detected on a wafer, comprising:

comparing portions of design data proximate positions of the defects in design data space with design data corresponding to different design based classifications, wherein the design data corresponding to the different design based classifications and the different design based classifications are stored in a data structure;

determining if the design data in the portions is at least similar to the design data corresponding to the different design based classifications based on results of said comparing;

assigning to the defects the design based classifications corresponding to the design data that is at least similar to the design data in the portions; and

storing results of said assigning in a storage medium.

58. The method of claim 57, wherein the computer-implemented method is performed by an inspection system used to detect the defects.

59. The method of claim 57, wherein the computer-implemented method is performed by a system other than an inspection system used to detect the defects.

60. The method of claim 57, further comprising monitoring hot spots in the design data based on the results of said assigning.

61. The method of claim 57, wherein the design data corresponding to the different design based classifications is identified by grouping defects detected on one or more other wafers based on portions of the design data proximate positions of the defects detected on the one or more other wafers in the design data space.

62. The method of claim 57, wherein the defects were detected in an inspection process, the method further comprising reviewing locations on the wafer at which one or more patterns of interest in the design data are printed, determining based on results of said reviewing if defects should have been detected at the locations of the one or more patterns of interest, and altering the inspection process to improve one or more defect capture rates.

63. The method of claim 57, further comprising determining if the defects are nuisance defects based on the design based classifications assigned to the defects and removing the nuisance defects from results of an inspection process in which the defects were detected to increase signal-to-noise ratio of the results of the inspection process.

64. The method of claim 57, further comprising determining a kill probability value for one or more of the defects.

65. The method of claim 57, further comprising determining if the design based classifications assigned to the defects correspond to systematic defects that are visible to a review system and sampling the defects for review by selecting only the defects that are visible to the review system for the review.

66. The method of claim 57, further comprising determining one or more patterns of interest in the design data by identifying one or more features in the design data indicative of a pattern dependent defect.

67. The method of claim 57, wherein the design based classifications identify one or more polygons in the design data on which the defects are located or located near the defects.

68. The method of claim 57, wherein the design based classifications identify locations of the defects in one or more polygons in the design data.

69. The method of claim 57, wherein the data structure comprises a library containing examples of the design data organized by technology, process, or some combination thereof.

70. The method of claim 57, further comprising separating the design data proximate the positions of the defects into the design data in areas around the defects and the design data in areas on which the defects are located.

71. The method of claim 57, further comprising monitoring systematic defects, potential systematic defects, or some combination thereof over time using the results of said assigning.

72. The method of claim 57, further comprising determining a kill probability value for one or more of the design based classifications based on one or more attributes of the design data corresponding to the design based classifications.

73. The method of claim 57, further comprising determining a kill probability value for one or more of the defects based on one or more attributes of the design data corresponding to the design based classifications assigned to the one or more of the defects.

74. The method of claim 57, further comprising monitoring kill probability values for one or more of the design based classifications and assigning to the defects the kill probability values for the design based classifications assigned to the defects.

75. The method of claim 57, wherein dimensions of at least some of the portions are different.

76. The method of claim 57, wherein the design data in the portions comprises design data for more than one design layer.

77. The method of claim 57, further comprising determining the positions of the defects in the design data space by comparing data acquired by an inspection system for alignment sites on the wafer with data for predetermined alignment sites.

78. The method of claim 57, further comprising determining the positions of the defects in the design data space by comparing data acquired by an inspection system during detection of the defects to locations in the design data determined by review.

79. The method of claim 57, wherein said assigning comprises assigning to the defects the design based classifications corresponding to the design data that is at least similar to the design data in the portions and that has one or more attributes that are at least similar to one or more attributes of the design data in the portions.

80. The method of claim 79, wherein the one or more attributes comprise one or more attributes of results of an inspection in which the defects were detected, one or more parameters of the inspection, or some combination thereof.

81. The method of claim 57, wherein the design data proximate the positions of the defects comprises the design data on which the defects are located.

82. The method of claim 57, wherein the design data proximate the positions of the defects comprises the design data around the positions of the defects.

83. The method of claim 57, further comprising binning the defects assigned one or more of the design based classifications in groups such that the positions of the defects in each of the groups with respect to polygons in the portions of the design data proximate the positions of the defects are at least similar.

84. The method of claim 57, further comprising selecting at least some of the defects for review based on the results of said assigning.

85. The method of claim 57, further comprising generating a process for sampling the defects for review based on the results of said assigning.

86. The method of claim 57, further comprising altering a process for inspecting the wafer based on the results of said assigning.

87. The method of claim 57, further comprising altering a process for inspection of the wafer during the inspection based on results of the inspection.

88. The method of claim 57, further comprising altering a metrology process for the wafer based on the results of said assigning.

89. The method of claim 57, further comprising altering a sampling plan for a metrology process for the wafer based on the results of said assigning.

90. The method of claim 57, further comprising prioritizing one or more of the design based classifications and optimizing one or more processes to be performed on wafers on which the design data will be printed based on results of said prioritizing.

91. The method of claim 57, further comprising determining a root cause of the defects based on the design based classifications assigned to the defects.

92. The method of claim 57, further comprising determining a root cause of at least some of the defects by mapping the at least some of the defects to experimental process window results.

93. The method of claim 57, further comprising determining a root cause of at least some of the defects by mapping the at least some of the defects to simulated process window results.

94. The method of claim 57, further comprising determining a root cause corresponding to one or more of the defect based classifications and assigning a root cause to the defects based on the root cause corresponding to the defect based classifications assigned to the defects.

95. The method of claim 57, further comprising determining a percentage of a die formed on the wafer impacted by the defects to which one or more of the design based classifications are assigned.

96. The method of claim 57, further comprising determining a pattern of interest in the design data corresponding to at least one of the design based classifications and determining a ratio of number of the defects to which the at least one of the design based classifications have been assigned to number of locations of the pattern of interest on the wafer.

97. The method of claim 57, further comprising determining one or more patterns of interest in the design data corresponding to at least one of the design based classifications and determining a ratio of number of the defects to which the at least one of the design based classifications have been assigned to number of locations of the one or more patterns of interest in the design data.

98. The method of claim 57, further comprising determining a pattern of interest in the design data corresponding to at least one of the design based classifications, determining a percentage of a die formed on the wafer in which the defects to which the at least one of the design based classifications have been assigned are located, and assigning a priority to the pattern of interest based on the percentage.

99. The method of claim 57, further comprising prioritizing one or more of the design based classifications by number of total design instances on the wafer at which the defects to which the one or more of the design based classifications have been assigned are detected.

100. The method of claim 57, further comprising prioritizing one or more of the design based classifications by number of design instances on a reticle, used to print the design data on the wafer, at which the defects to which the one or more of the design based classifications have been assigned are detected at least once.

101. The method of claim 57, further comprising determining reticle-based marginality for one or more of the design based classifications based on number of locations on a reticle at which the defects to which the one or more of the design based classifications have been assigned were detected and total number of portions of the design data printed on the reticle that are similar to the portions of the design data proximate the positions of the defects to which the one or more of the design based classifications have been assigned.

102. The method of claim 57, further comprising converting the portions of the design data proximate the positions of the defects to first bitmaps prior to said comparing and converting the design data corresponding to the design based classifications to second bitmaps prior to said comparing, wherein said comparing comprises comparing the first bitmaps with the second bitmaps.

103. A method for altering an inspection process for wafers, comprising:

reviewing locations on the wafer at which one or more patterns of interest in the design data are printed;

determining based on results of said reviewing if defects should have been detected at the locations of the one or more patterns of interest; and

altering the inspection process to improve one or more defect capture rates for defects located in at least some of the one or more patterns of interest.

104. The method of claim 103, wherein said altering comprises altering an optics mode of an inspection system used to perform the inspection process.

105. The method of claim 103, further comprising determining an optics mode of an inspection system used to perform the inspection process based on results of said determining.

106. The method of claim 103, wherein said altering comprises altering the inspection process to suppress noise in results of the inspection process.

107. The method of claim 103, wherein said altering comprises altering the inspection process to reduce detection of defects not of interest.

108. The method of claim 103, wherein said altering comprises altering an algorithm used in the inspection process.

109. The method of claim 103, wherein said altering comprises altering one or more parameters of an algorithm used in the inspection process.

110. A system configured to display and analyze design and defect data, comprising:

a user interface configured for displaying a design layout for a semiconductor device, inline inspection data acquired for a wafer on which at least a portion of the semiconductor device is formed, and electrical test data acquired for the wafer; and

a processor configured for analyzing one or more of the design layout, the inline inspection data, and the electrical test data upon receiving an instruction to perform said analyzing from a user via the user interface.

111. The system of claim 110, wherein the electrical test data comprises logic bitmap data.

112. The system of claim 110, wherein the user interface is further configured for displaying overlay of at least two of the design layout, the inline inspection data, and the electrical test data.

113. The system of claim 110, wherein the user interface is further configured for displaying overlay of at least two of the design layout, the inline inspection data, and the electrical test data, and wherein the electrical test data comprises logic bitmap data.

114. The system of claim 110, wherein the processor is further configured for determining defect density in design data space upon receiving an instruction to perform said determining from the user via the user interface.

115. The system of claim 110, wherein the processor is further configured to perform defect sampling for review upon receiving an instruction to perform the defect sampling from the user via the user interface.

116. The system of claim 110, wherein the processor is further configured for grouping defects based on similarity of the design layout proximate to positions of the defects in design data space upon receiving an instruction to perform the grouping from the user via the user interface.

117. A computer-implemented method for determining a root cause of electrical defects detected on a wafer, comprising:

determining positions of the electrical defects in design data space;

determining if the positions of a portion of the electrical defects define a spatial signature corresponding to one or more process conditions;

if the positions of the portion of the electrical defects define a spatial signature that corresponds to the one or more process conditions, identifying the root cause of the portion of the electrical defects as the one or more process conditions; and

storing results of said identifying in a storage medium.

118. A computer-implemented method for selecting defects detected on a wafer for review, comprising:

identifying one or more zones on the wafer, wherein the one or more zones are associated with positions of one or more defect types on the wafer;

selecting defects detected in only the one or more zones for review; and

storing results of said selecting in a storage medium.

119. A computer-implemented method for evaluating one or more yield related processes for design data, comprising:

identifying potential failures in the design data using rule checking;

determining one or more attributes of the potential failures;

determining if the potential failures are detectable based on the one or more attributes;

determining which of a plurality of different inspection systems is most suitable for detecting the potential failures based on the one or more attributes; and

storing results of said determining which of the plurality of different inspection systems is most suitable for said detecting in a storage medium.

120. The method of claim 119, further comprising selecting one or more parameters of the inspection system determined to be most suitable, wherein the parameters are selected based on the one or more attributes.

121. The method of claim 119, further comprising determining an impact of the potential failures on yield of devices fabricated with the design data.